RECTIFIER CIRCUIT AND SEMICONDUCTOR DEVICE USING THE SAME

• US 20120075897A1
• Filed: 09/15/2011
• Published: 03/29/2012
• Est. Priority Date: 09/27/2010
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: FUJITA, Masashi
• Granted Patent: US 8,792,260 B2
• Time in Patent Office: Days
• US Class Current: 363/127
• CPC Class Codes: H02M 7/05 Capacitor coupled rectifiers
• CPC Class Codes: H02M 7/217 using semiconductor devices only
• CPC Class Codes: H02M 7/2195 the switches being synchronously commutated at the same frequency of the AC input voltage
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

An object is to provide a rectifier circuit of which the drop in the output voltage by the threshold voltage of a transistor used as a rectifier element is suppressed. Another object is to provide a rectifier circuit whose variations in the output voltage are suppressed even in the case where the amplitude of input AC voltage varies greatly. A transistor may be used as a rectifier element in such a way that a gate electrode of the transistor is connected to a second electrode of the transistor through a capacitor, and the potential of the gate electrode is held to be higher than the potential of the second electrode by a difference greater than or equal to the threshold voltage.

Claims

1. A rectifier circuit comprising:

a first transistor whose gate electrode is connected to a node 2, whose first electrode is connected to a node 1, and whose second electrode is connected to a second terminal;

a second transistor whose gate electrode is connected to the node 1, whose first electrode is connected to the node 2, and whose second electrode is connected to a first terminal;

a third transistor whose gate electrode is connected to the node 1, whose first electrode is connected to a node 3, and whose second electrode is connected to the node 1;

a first capacitor whose first electrode is connected to the first terminal and whose second electrode is connected to the node 1; and

a second capacitor whose first electrode is connected to the second terminal and whose second electrode is connected to the node 2,

wherein the first transistor, the second transistor, and the third transistor are n-channel enhancement transistors, and

wherein AC voltage input to the first terminal and the second terminal is rectified to DC voltage and the DC voltage is output to the node 3.

2. The rectifier circuit according to claim 1,

wherein each of the first transistor, the second transistor, and the third transistor comprises:

a gate electrode in contact with one surface of a gate insulating layer;

an oxide semiconductor layer that is in contact with the other surface of the gate insulating layer and is overlapped with the gate electrode;

a source electrode and a drain electrode, which are in contact with the oxide semiconductor layer and include end portions that overlap with the gate electrode; and

an oxide insulating layer that is in contact with the oxide semiconductor layer and is overlapped with a channel formation region.

3. The rectifier circuit according to claim 1, further comprising:

a first limiting circuit provided between the first terminal and the node 1; and

a second limiting circuit provided between the second terminal and the node 2.

4. An RFID tag comprising the rectifier circuit according to claim 1.

5. A rectifier circuit comprising:

a first transistor whose gate electrode is connected to a node 2, whose first electrode is connected to a node 1, and whose second electrode is connected to a second terminal;

a second transistor whose gate electrode is connected to the node 1, whose first electrode is connected to the node 2, and whose second electrode is connected to a first terminal;

a third transistor whose gate electrode is connected to the node 1, whose first electrode is connected to a node 3, and whose second electrode is connected to the node 1;

a fourth transistor whose gate electrode is connected to the node 3, whose first electrode is connected to a fourth terminal, and whose second electrode is connected to the node 3;

a first capacitor whose first electrode is connected to the first terminal and whose second electrode is connected to the node 1;

a second capacitor whose first electrode is connected to the second terminal and whose second electrode is connected to the node 2;

a third capacitor whose first electrode is connected to the fourth terminal and whose second electrode is grounded; and

a fourth capacitor whose first electrode is connected to the node 2 and whose second electrode is connected to the node 3,

wherein the first transistor, the second transistor, the third transistor, and the fourth transistor are n-channel enhancement transistors, and

wherein AC voltage input to the first terminal and the second terminal is rectified to DC voltage and the DC voltage is output to the fourth terminal.

6. The rectifier circuit according to claim 5,

wherein each of the first transistor, the second transistor, the third transistor, and the fourth transistor comprises:

a gate electrode in contact with one surface of a gate insulating layer;

an oxide semiconductor layer that is in contact with the other surface of the gate insulating layer and is overlapped with the gate electrode;

a source electrode and a drain electrode, which are in contact with the oxide semiconductor layer and include end portions that overlap with the gate electrode; and

an oxide insulating layer that is in contact with the oxide semiconductor layer and is overlapped with a channel formation region.

7. The rectifier circuit according to claim 5, further comprising:

a first limiting circuit provided between the first terminal and the node 1; and

a second limiting circuit provided between the second terminal and the node 2.

8. An RFID tag comprising the rectifier circuit according to claim 5.

9. A rectifier circuit comprising:

a first transistor whose gate electrode is connected to a node 2, whose first electrode is connected to a node 1, and whose second electrode is connected to a second terminal;

a second transistor whose gate electrode is connected to the node 1, whose first electrode is connected to the node 2, and whose second electrode is connected to a first terminal;

a third transistor whose gate electrode is connected to the node 1, whose first electrode is connected to a node 3, and whose second electrode is connected to the node 1;

a fourth transistor whose gate electrode is connected to the node 3, whose first electrode is connected to a fourth terminal, and whose second electrode is connected to the node 3;

a fifth transistor whose gate electrode is connected to the node 3, whose first electrode is connected to the node 2, and whose second electrode is connected to the fourth terminal;

a first capacitor whose first electrode is connected to the first terminal and whose second electrode is connected to the node 1;

a second capacitor whose first electrode is connected to the second terminal and whose second electrode is connected to the node 2;

a third capacitor whose first electrode is connected to the fourth terminal and whose second electrode is grounded; and

a fourth capacitor whose first electrode is connected to the node 2 and whose second electrode is connected to the node 3,

wherein the first transistor, the second transistor, the third transistor, the fourth transistor, and the fifth transistor are n-channel enhancement transistors, and

wherein AC voltage input to the first terminal and the second terminal is rectified to DC voltage and the DC voltage is output to the fourth terminal.

10. The rectifier circuit according to claim 9,

wherein each of the first transistor, the second transistor, the third transistor, the fourth transistor, and the fifth transistor comprises:

a gate electrode in contact with one surface of a gate insulating layer;

an oxide semiconductor layer that is in contact with the other surface of the gate insulating layer and is overlapped with the gate electrode;

a source electrode and a drain electrode, which are in contact with the oxide semiconductor layer and include end portions that overlap with the gate electrode; and

an oxide insulating layer that is in contact with the oxide semiconductor layer and is overlapped with a channel formation region.

11. An RFID tag comprising the rectifier circuit according to claim 9.