Cache with Multiple Access Pipelines

• US 20120079204A1
• Filed: 08/18/2011
• Published: 03/29/2012
• Est. Priority Date: 09/28/2010
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Damodaran, Raguram, Anderson, Timothy David, Chachad, Abhijeet Ashok, Tran, Jonathan (Son) Hung, Agarwala, Sanjive
• Granted Patent: US 8,904,115 B2
• Time in Patent Office: Days
• US Class Current: 711/130
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: G06F 11/1064 in cache or content addressable memories
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 12/0815 Cache consistency protocols
• CPC Class Codes: G06F 12/1081 for peripheral access to main memory, e.g. direct memory access [DMA]
• CPC Class Codes: G06F 12/12 Replacement control
• CPC Class Codes: G06F 13/1605 based on arbitration arbitration in handling access to a common bus or bus system G06F13/36
• CPC Class Codes: G06F 13/1652 in a multiprocessor architecture interprocessor communication using common memory G06F15/167
• CPC Class Codes: G06F 13/1657 Access to multiple memories
• CPC Class Codes: G06F 13/1663 Access to shared memory
• CPC Class Codes: G06F 13/18 based on priority control G06F13/1605 takes precedence
• CPC Class Codes: G06F 13/364 using independent requests or grants, e.g. using separated request and grant lines
• CPC Class Codes: G06F 2212/1021 Hit rate improvement
• CPC Class Codes: G06F 2212/1032 Reliability improvement, data loss prevention, degraded operation etc
• CPC Class Codes: G06F 2212/221 Static RAM
• CPC Class Codes: G06F 2212/2532 comprising a plurality of modules
• CPC Class Codes: G06F 2212/283 Plural cache memories
• CPC Class Codes: G06F 2212/608 Details relating to cache mapping
• CPC Class Codes: G06F 7/483 Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers G06F7/4806, G06F7/4824, G06F7/49, G06F7/491, G06F7/544 take precedence
• CPC Class Codes: G06F 9/3012 : Organisation of register space, e.g. banked or distributed register file
• CPC Class Codes: H03K 19/0016 : by using a control or a clock signal, e.g. in order to apply power supply
• CPC Class Codes: H03K 21/00 : Details of pulse counters or frequency dividers
• CPC Class Codes: H03M 13/2903 : Methods and arrangements specifically for encoding, e.g. parallel encoding of a plurality of constituent codes
• CPC Class Codes: H03M 13/353 : Adaptation to the channel
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 : in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

Parallel pipelines are used to access a shared memory. The shared memory is accessed via a first pipeline by a processor to access cached data from the shared memory. The shared memory is accessed via a second pipeline by a memory access unit to access the shared memory. A first set of tags is maintained for use by the first pipeline to control access to the cache memory, while a second set of tags is maintained for use by the second pipeline to access the shared memory. Arbitrating for access to the cache memory for a transaction request in the first pipeline and for a transaction request in the second pipeline is performed after each pipeline has checked its respective set of tags.

Claims

1. A method of operating a cache having shared memory and tags, the method comprising:

accessing the cache via a first pipeline for use by a processor to access cached data from the shared memory;

accessing the cache via a second pipeline for use by a memory access unit to access the shared memory;

maintaining a first set of tags for use by the first pipeline to control access to the shared memory;

maintaining a second set of tags for use by the second pipeline to access the shared memory; and

arbitrating for access to the shared memory for a transaction request in the first pipeline and for a transaction request in the second pipeline after each pipeline has checked its respective set of tags, wherein a winner of the arbitration is granted access to the shared memory.

2. The method of claim 1, further comprising:

stalling the first pipeline in response to checking the first set of tags for a first transaction request; and

allowing a second transaction in the second pipeline to access to the shared memory while the first pipeline is stalled.

3. The method of claim 1, further comprising maintaining duplicate buffers and registers needed by the first pipeline and by the second pipeline to access the shared memory.

4. The method of claim 1, wherein a portion of the accesses by the memory access unit perform snooping of cache memory by using the second set of tags.

5. The method of claim 1, wherein the first set of tags and the second set of tags are duplicated.

6. The method of claim 1, further comprising dynamically changing a fairness weighting to be used during arbitration.

7. A method of operating a shared resource, the method comprising:

accessing the shared resource via a first pipeline for use by a processor to access the shared resource;

accessing the shared resource via a second pipeline for use by a memory access unit to access the shared resource;

maintaining a set of tags for use by the first pipeline to control access to the shared resource; and

arbitrating for access to the shared resource for a transaction request in the first pipeline and for a transaction request in the second pipeline after the first pipeline has checked its set of tags, wherein a winner of the arbitration is granted access to the shared resource.

8. The method of claim 7, further comprising:

stalling the first pipeline in response to checking the set of tags for a first transaction request; and

allowing a second transaction request in the second pipeline to access to the shared resource while the first pipeline is stalled.

9. A digital system comprising:

a shared resource;

a first access pipeline coupled to the shared resource, the first pipeline being configured to receive a first transaction request from a first requester for access to the shared resource, wherein the first pipeline includes a stall stage that is configured to check for a stall condition;

a second access pipeline coupled to the shared resource, the second pipeline being configured to receive a second transaction request from a second requester for access to the shared resource; and

arbitration logic configure to control access to the shared resource coupled to the first pipeline and to the second pipeline, wherein the arbitration logic is coupled to the first pipeline after the stall stage.

10. The system of claim 9, wherein the shared resource comprises a cache subsystem having a shared memory and access tags.

11. The system of claim 10, wherein the stall stage of the first pipeline is coupled to the access tags, such that the first pipeline is configured to stall when the access tags indicate a miss in response to the first transaction request.

12. The system of claim 11, wherein the second pipeline includes a check stage that is configured to check the access tags, and wherein the arbitration logic is coupled to the second pipeline after the check stage.

13. The system of claim 12, wherein the access tags comprise a first set of tags for use by the first pipeline and a second set of tags for use by the second pipeline.

14. The system of claim 9, further comprising weighting logic coupled to the arbitration logic, wherein the arbitration logic is configured to grant access to the shared resource in response to the weighting logic.

15. The method of claim 14, wherein the weighting logic is operable to be dynamically updated while the system is in operation.