Coherency control with writeback ordering

• US 20120079211A1
• Filed: 09/12/2011
• Published: 03/29/2012
• Est. Priority Date: 09/28/2010
• Status: Active Grant

• Current Assignee: Arm Ltd. (United Kingdom) (SoftBank Group Corp.)
• Original Assignee: Arm Ltd. (United Kingdom) (SoftBank Group Corp.)
• Inventors: Laycock, Christopher William, Harris, Antony John, Mathewson, Bruce James, Biles, Stuart David
• Granted Patent: US 8,589,631 B2
• Time in Patent Office: Days
• US Class Current: 711/143
• CPC Class Codes: G06F 12/0833 in combination with broadcast means (e.g. for invalidation or updating)
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Interconnect circuitry configured to provide routes for interconnecting several initiator devices and at least one recipient device including a memory. At least one of the initiator devices has a cache for storing a local copy of a subset of data items stored in the memory. The interconnect circuitry includes: a plurality of input ports and at least one output port; a plurality of paths for transmitting the transaction requests between the inputs and the at least one output; coherency control circuitry for maintaining an order in which at least some of the transaction requests to a same data storage location proceed through the interconnect circuitry. The interconnect circuitry is configured not to control the writeback transaction requests with the coherency control circuitry, such that the writeback transaction requests proceed independently of transaction requests routed through the coherency control circuitry.

Claims

1. Interconnect circuitry for a data processing apparatus, said interconnect circuitry being configured to provide routes for interconnecting a plurality of initiator devices and at least one recipient device, at least one of said at least one recipient device comprising at least one memory for storing at least one data item to be processed by said processing apparatus, at least one of said plurality of initiator devices comprising a cache for storing a local copy of a subset of said data items stored in said at least one memory said interconnect circuitry comprising:

a plurality of input ports for receiving transaction requests from said plurality of initiator devices;

at least one output port for outputting transaction requests to said at least one recipient device;

a plurality of paths for transmitting said transaction requests between said plurality of inputs and said at least one output;

coherency control circuitry for maintaining an order in which at least some of said transaction requests to a same data storage location proceed through said interconnect circuitry in order to maintain coherency of data items processed by said data processing apparatus;

said interconnect circuitry being configured not to control a writeback transaction requests with said coherency control circuitry, such that said writeback transaction requests proceed independently of transaction requests routed through said coherency control circuitry, said writeback transaction requests being write transaction requests received from said at least one initiator device comprising said cache and being for updating said at least one memory with a locally stored updated value of one of said data items.

2. Interconnect circuitry according to claim 1, wherein said transaction requests comprise read transaction requests and write transaction requests, at least some of said read transaction requests being controlled by said coherency control circuitry.

3. Interconnect circuitry according to claim 2, wherein all of said read transaction requests are controlled by said coherency control circuitry.

4. Interconnect circuitry according to claim 2, wherein at least some of said write transaction requests but not said writeback transaction requests are controlled by said coherency control circuitry.

5. Interconnect circuitry according to claim 2, said transaction requests further comprising cache maintenance requests, said cache maintenance requests being transmitted through said coherency control circuitry.

6. Interconnect circuitry according to claim 1, wherein said plurality of paths comprise read paths for transmitting read transaction requests and write paths for transmitting write transaction requests.

7. Interconnect circuitry according to claim 6, said transaction requests further comprising cache maintenance requests, said cache maintenance requests being transmitted through said coherency control circuitry, wherein said cache maintenance requests are transmitted along said read paths.

8. Interconnect circuitry according to claim 1, wherein said write and read paths that pass through said coherency control circuitry pass through one of at least one point of serialisation.

9. Interconnect circuitry according to claim 1, wherein said coherency control circuitry is configured to maintain coherency of data items processed by said data processing apparatus, by generating querying transactions for avoiding any coherency conflicts between locally stored data within a cache on any one of said plurality of initiator devices and a transaction request received from another of said plurality of initiator devices.

10. Interconnect circuitry according to claim 1, wherein at least one of said input ports comprises a data store associated with it for storing a local copy of a data item being processed by said initiator connected to said at least one input port, coherency of said local copy of said data item being controlled by said coherency control circuitry.

11. Interconnect circuitry according to claim 10, wherein said data store comprises a small cache.

12. Interconnect circuitry according to claim 1, wherein at least one of said input ports comprises means for holding a received transaction request, said at least one input port being configured to transmit at least one query related to said held transaction request to at least one of said other initiator devices, and in response to receiving a response to associate said response with said held transaction request and to transmit them further.

13. Interconnect circuitry according to claim 1, wherein said at least one recipient device is configured to receive both write and read transaction requests and to process said read and write transaction requests in an order determined by a memory controller, said coherency control circuitry being configured not to transmit a read transaction request further until said coherency control circuitry can guarantee completion of said read transaction request.

14. Interconnect circuitry according to claim 1, wherein said coherency control circuitry is configured not to transmit a write unique transaction to a storage location before issuing at least one query to at least one of said initiators that may store a local copy of a data item stored in said storage location and to only transmit said write unique transaction further when it is clear from a response to said at least one query that said data will be retrieved by said write unique transaction, wherein write unique transactions are write transactions to a storage location that ensure that any local copy of a data item stored in said storage location is rendered invalid.

18. A data processing apparatus comprising:

a plurality of initiators configured to issue a plurality of transaction requests;

at least one recipient configured to receive said plurality of transaction requests, at least one of said at least one recipient comprising a memory for storing data items processed by said data processing apparatus;

at least one of said plurality of initiators comprising an initiator according to claim 15; and

interconnect circuitry according to claim 1.

19. A data processing apparatus according to claim 18, said interconnect circuitry being interconnect circuitry, wherein at least one of said input ports comprises a data store associated with it for storing a local copy of a data item being processed by said initiator connected to said at least one input port, coherency of said local copy of said data item being controlled by said coherency control circuitry, said initiator connected to said at least one port comprising an initiator device according to said initiator device being configured to issue write unique transactions, write unique transactions being write transactions to a storage location, wherein the write unique transaction ensures that any local copy of a data item stored in said storage location is rendered invalid, said initiator being configured not to issue a writeback transaction while a write unique transaction is pending.

20. A data processing apparatus according, to claim 18, wherein at least one of said initiators does not comprise a cache.

15. An initiator device comprising:

a cache for storing a local copy of at least one of said data items stored in said memory, said at least one initiator being configured to maintain coherency of said locally stored at least one data item, by in response to said locally stored data item being updated, marking said locally stored data item as dirty until said at least one initiator has performed a writeback operation and written said updated data item to said memory;

at least one port for transmitting transaction requests to at least one recipient device, and for receiving data and query requests querying said cache;

wherein

said initiator device is configured not to issue a response to receipt of a request querying a state of a storage location within said cache if a writeback transaction to said storage location is pending, and to issue said response when said pending writeback transaction has completed, said writeback transaction request being a request issued by said initiator device to update said memory with a value of a data item stored in said cache that has itself been updated, such that said memory stores a current value of said data item.

16. An initiator device according to claim 15, said initiator device being configured to issue write unique transactions, write unique transactions being write transactions to a storage location, wherein the write unique transaction ensures that any local copy of a data item stored in said storage location is rendered invalid, said initiator being configured not to issue a writeback transaction while a write unique transaction is pending.

17. An initiator device according to claim 15, said initiator device comprises a cache and is configured to issue write unique transactions, write unique transactions being write transactions to a location where said location stores the only local copy of a data item, said initiator being configured not to issue said write unique transactions in response to any of said lines in said cache being dirty.

21. A method of maintaining coherency comprising the steps of:

issuing a writeback request from an initiator comprising a cache to a memory via an interconnect, said writeback transaction request being a write transaction request for updating said memory with an updated value of a data item stored locally on said cache;

allowing said writeback request to proceed through said interconnect independently of transaction requests routed through a coherency control circuitry, in response to receipt of a request at said initiator querying a state of a storage location in said cache for which said writeback transaction is pending, not responding to said querying request until said pending writeback transaction has completed.