APPARATUS, METHOD, AND SYSTEM FOR IMPLEMENTING MICRO PAGE TABLES

• US 20120079232A1
• Filed: 09/24/2010
• Published: 03/29/2012
• Est. Priority Date: 09/24/2010
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Hinton, Glenn, Parthasarathy, Rajesh, Zimmerman, David, Smith, Larry O., Moga, Adrian C., Downer, Wayne A., Chappell, Robert S., Parthasarathy, Madhavan, Swaminathan, Muthukumar, Ramanujan, Raj, Cape, Scott J.
• Granted Patent: US 8,838,935 B2
• Time in Patent Office: Days
• US Class Current: 711/207
• CPC Class Codes: G06F 12/023 Free address space management
• CPC Class Codes: G06F 12/0292 using tables or multilevel address translation means G06F12/023 takes precedence; address translation in virtual memory systems G06F12/10
• CPC Class Codes: G06F 12/06 Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication G06F12/08 takes precedence
• CPC Class Codes: G06F 12/1009 using page tables, e.g. page table structures
• CPC Class Codes: G06F 12/1027 using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
• CPC Class Codes: G06F 2212/1028 Power efficiency
• CPC Class Codes: G06F 2212/1041 Resource optimization
• CPC Class Codes: G06F 2212/151 Emulated environment, e.g. virtual machine
• CPC Class Codes: G06F 2212/205 Hybrid memory, e.g. using both volatile and non-volatile memory
• CPC Class Codes: G06F 2212/651 Multi-level translation tables
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

An apparatus, method, machine-readable medium, and system are disclosed. In one embodiment the apparatus is a micro-page table engine that includes logic that is capable of receiving a memory page request for a page in global memory address space. The apparatus also includes a translation lookaside buffer (TLB) that is capable of storing one or more memory page address translations. Additionally, the apparatus also has a page miss handler capable of performing a micro physical address lookup in a page miss handler tag table in response to the TLB not storing the memory page address translation for the page of memory referenced by the memory page request. The apparatus also includes memory management logic that is capable of managing the page miss handler tag table entries. The micro-page table engine allows the TLB to be an agent that determines whether data in a two-level memory hierarchy is in a hot region of memory or in a cold region of memory. When data is in the cold region of memory, the micro-page table engine fetches the data to the hot memory and a hot memory block is then pushed out to the cold memory area.

Claims

1. A micro page table engine apparatus comprising:

logic to receive a memory page request for a page in global memory address space;

a translation lookaside buffer (TLB) to store one or more memory page address translations;

a page miss handler logic to perform a micro physical address lookup in a page miss handler tag table in response to the TLB not storing the memory page address translation for the page of memory referenced by the memory page request; and

a memory management logic to manage entries in the page miss handler tag table.

2. The apparatus of claim 1, wherein the page miss handler tag table is located in a hidden area of a system memory accessible by the micro page table engine.

3. The apparatus of claim 2, wherein the page miss handler tag table is fully associative and has a separate entry for a plurality of pages of the system memory.

4. The apparatus of claim 3, wherein micro physical address space is divided into a cold region and a hot region.

5. The apparatus of claim 4, wherein the memory management logic is operable to free a first memory page in the hot region by transferring data from the first memory page to a second memory page in the cold region.

6. The apparatus of claim 5, further comprising logic to transfer data from a third memory page in the cold region to the first memory page in the hot region in response to the received memory request targeting the third memory page in the cold region.

7. The apparatus of claim 6, wherein the micro physical address space spans two portions of physical memory, a physical memory A and a physical memory B, wherein the micro physical address space of physical memory A comprises the hot region and the micro physical address space of physical memory B comprises the cold region.

8. The apparatus of claim 3, wherein the micro physical address space comprises a shared portion of micro physical address space that is shared between a plurality of processors, and a plurality of non-shared portions of micro physical address space, wherein each of the plurality of processors receives one of the non-shared portions.

9. A method comprising:

receiving a memory page request for a page in global memory address space;

storing one or more memory page address translations in a translation lookaside buffer (TLB);

performing a micro physical address lookup in a page miss handler tag table in response to the TLB not storing the memory page address translation for the page of memory referenced by the memory page request; and

managing entries in the page miss handler tag table.

10. The method of claim 9, wherein the page miss handler tag table is located in a hidden area of a system memory accessible by the micro page table engine.

11. The method of claim 10, wherein the page miss handler tag table is fully associative and has a separate entry for every page of the system memory.

12. The method of claim 11, wherein micro physical address space is divided into a cold region and a hot region.

13. The method of claim 12, further comprising:

freeing a first memory page in the hot region by transferring data from the first memory page to a second memory page in the cold region.

14. The method of claim 13, further comprising:

transferring data from a third memory page in the cold region to the first memory page in the hot region in response to the received memory request targeting the third memory page in the cold region.

15. The method of claim 14, wherein the micro physical address space spans two portions of physical memory, a physical memory A and a physical memory B, wherein physical memory A and physical memory B comprise different memory technologies, and wherein the micro physical address space of physical memory A comprises the hot region and the micro physical address space of physical memory B comprises the cold region.

16. The method of claim 11, wherein the micro physical address space comprises a shared portion of micro physical address space that is shared between a plurality of processors, and a plurality of non-shared portions of micro physical address space, wherein each of the plurality of processors receives one of the non-shared portions.

17. A machine-readable medium having stored thereon instructions, which if executed by a machine causes the machine to perform a method comprising:

receiving a memory page request for a page in global memory address space;

storing one or more memory page address translations in a translation lookaside buffer (TLB);

performing a micro physical address lookup in a page miss handler tag table in response to the TLB not storing the memory page address translation for the page of memory referenced by the memory page request; and

managing entries in the page miss handler tag table.

18. The machine-readable medium of claim 17, wherein the page miss handler tag table is located in a hidden area of a system memory accessible by the micro page table engine.

19. The machine-readable medium of claim 18, wherein the page miss handler tag table is fully associative and has a separate entry for every page of the system memory.

20. The machine-readable medium of claim 19, wherein micro physical address space is divided into a cold region and a hot region.

21. The machine-readable medium of claim 20, wherein the performed method further comprises:

freeing a first memory page in the hot region by transferring data from the first memory page to a second memory page in the cold region.

22. The machine-readable medium of claim 21, wherein the performed method further comprises:

transferring data from a third memory page in the cold region to the first memory page in the hot region in response to the received memory request targeting the third memory page in the cold region.

23. The machine-readable medium of claim 22, wherein the micro physical address space spans two portions of physical memory, a physical memory A and a physical memory B, wherein physical memory A and physical memory B comprise different memory technologies, and wherein the micro physical address space of physical memory A comprises the hot region and the micro physical address space of physical memory B comprises the cold region.

24. The machine-readable medium of claim 19, wherein the micro physical address space comprises a shared portion of micro physical address space that is shared between a plurality of processors, and a plurality of non-shared portions of micro physical address space, wherein each of the plurality of processors receives one of the non-shared portions.

25. A system, comprising:

a first memory, wherein the first memory includes a hidden portion for storing at least a page miss handler tag table; and

a first processor, the first processor including;

logic to receive a memory page request for a page in global memory address space;

a translation lookaside buffer (TLB) to store one or more memory page address translations;

a page miss handler logic to perform a micro physical address lookup in a page miss handler tag table in response to the TLB not storing the memory page address translation for the page of memory referenced by the memory page request; and

a memory management logic to manage entries in the page miss handler tag.