OPPORTUNISTIC DECODING IN MEMORY SYSTEMS

• US 20120079355A1
• Filed: 09/27/2010
• Published: 03/29/2012
• Est. Priority Date: 09/27/2010
• Status: Active Grant

• Current Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Original Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Inventors: Patapoutian, Ara, Rub, Bernardo, Buch, Bruce
• Granted Patent: US 8,627,175 B2
• Time in Patent Office: Days
• US Class Current: 714/780
• CPC Class Codes: G06F 11/1008 in individual solid state devices G06F11/1004 takes precedence
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 29/844 by splitting the decoders in stages
• CPC Class Codes: H03M 13/1108 Hard decision decoding, e.g. bit flipping, modified or weighted bit flipping
• CPC Class Codes: H03M 13/1111 Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms
• CPC Class Codes: H03M 13/3707 Adaptive decoding and hybrid decoding, e.g. decoding methods or techniques providing more than one decoding algorithm for one code
• CPC Class Codes: H03M 13/45 Soft decoding, i.e. using symbol reliability information H03M13/41 takes precedence
• CPC Class Codes: H03M 13/451 using a set of candidate code words, e.g. ordered statistics decoding [OSD]
• CPC Class Codes: H03M 13/458 by updating bit probabilities or hard decisions in an iterative fashion for convergence to a final decoding result

Abstract

Approaches for decoding data read from memory cells of a nonvolatile, solid state memory involve attempting to decode hard data using a hard decoding process prior to a time that soft data is available to the decoder. The hard data includes information about the digital symbols stored in the memory cells without data confidence information. The soft data includes information about the digital symbols stored in the memory cells and data confidence information. In response to the hard decoding process failing to achieve convergence, after the soft data becomes available to the decoder, the soft data is decoded using a soft decoding process. The decoder generates an output of the decoded data after the hard decoding process or the soft decoding process achieves convergence.

Claims

1. A method of decoding data read from memory cells of a solid state, non-volatile memory, comprising:

receiving hard data that includes information about the data read from the memory cells without confidence information;

attempting to decode the hard data using a hard decoding process prior to a time that soft data is available to the decoder, the soft data including information about the data stored in the memory cells and data confidence information;

in response to the hard decoding process failing to achieve convergence, decoding the soft data using a soft decoding process; and

generating an output of the decoded data.

2. The method of claim 1, wherein:

the hard data is acquired from an initial read of the memory cells; and

the soft data is determined using information from an additional read operation of the memory cells.

3. The method of claim 2, wherein the additional read operation uses a reference voltage that is different from a reference voltage used for the initial read operation.

4. The method of claim 1, further comprising one or more of acquiring the information used to determine the soft data, determining the soft data, and decoding the soft data only if the hard decoding process fails to achieve convergence.

5. The method of claim 1, further comprising one or more of generating a request for acquisition of information used to determine the soft data, initiating a process to determine the soft data, and initiating the soft data decoding process regardless of success or failure of the hard decoding process to achieve convergence.

6. The method of claim 1, wherein one or both of the hard decoding process and the soft decoding process are LDPC decoding processes.

7. The method of claim 1, wherein one or both of the hard decoding process and the soft decoding process includes a plurality of decoding subprocesses, each of the decoding subprocesses capable of independently achieving convergence.

8. The method of claim 7, wherein each of the decoding subprocesses tests a different decoding hypothesis.

9. The method of claim 7, wherein each of the decoding subprocesses implements a different decoding algorithm.

10. The method of claim 1, further comprising, in response to the soft decoding process failing to achieve convergence, implementing an additional soft decoding process operating on additional soft data that is acquired from a different source of information than the soft decoding process.

11. A solid state, non-volatile memory system, comprising:

input circuitry configured to receive hard data, the hard data including information about data read from the memory cells without confidence information, and soft data, the soft data including information about the data read from the memory cells with confidence information;

decoder circuitry configured to implement a hard decoding process operating on the hard data during a time that the soft data associated is unavailable to the decoder circuitry and to implement a soft decoding process operating on the soft data at a later time when the soft data becomes available to the decoder; and

output circuitry configured to output the decoded data obtained from the hard decoding process or the soft decoding process.

12. The system of claim 11, further comprising controller circuitry configured to generate a request to acquire information used to determine the soft data, generate a request to determine the soft data, and generate a control signal to initiate the soft decoding process.

13. The system of claim 12, wherein the controller circuitry is configured to generate the request to acquire information used to determine the soft data, to generate the request to determine the soft data, and generate the control signal to initiate the soft decoding process only in response to the hard decoding process failing to achieve convergence.

14. The system of claim 12, wherein the controller circuitry is configured to generate the request to acquire the information used to determine the soft data, to generate the request to determine the soft data, and generate the control signal to initiate the soft decoding process regardless of whether or not the hard decoding process achieves convergence.

15. The system of claim 14, wherein the controller circuitry is configured to generate a control signal to terminate acquisition of the information used to determine the soft data, to generate a control signal to terminate the determination of the soft data and to generate a control signal to terminate the soft decoding process in response to the hard decoding process achieving convergence.

16. The system of claim 11, further comprising:

solid state memory cells; and

a detector, including

detector circuitry configured to perform read operations to read data stored in the memory cells and to output hard data including information about the data read from the memory cells without confidence information;

soft information circuitry configured to generate soft data, the soft data including information about the data read from the memory cells and confidence information.

17. The system of claim 16, wherein the soft information circuitry is configured to generate the soft data using noise statistics of the memory cell:

18. A method of decoding data read from memory cells of a solid state memory device, comprising:

implementing multiple decoding processes that operate concurrently to decode the data read from the memory cells, each of the multiple decoding processes capable of independently decoding the data to convergence and each of the multiple decoding processes implementing a different algorithm to decode the data and/or each of the multiple decoding processes decoding the data using a different decoding hypothesis; and

generating an output of the decoded data using a result of a decoding process of the multiple decoding processes that is first in time to achieve convergence.

19. The method of claim 18, further comprising, after the first-in-time decoding process achieves convergence, generating a signal to terminate decoding processes that have not yet achieved convergence.

20. A memory device configured to implement the method of claim 18.