SUSPECT LOGICAL REGION SYNTHESIS FROM DEVICE DESIGN AND TEST INFORMATION

• US 20120079439A1
• Filed: 06/01/2011
• Published: 03/29/2012
• Est. Priority Date: 09/27/2010
• Status: Active Grant

• Current Assignee: Teseda Corporation
• Original Assignee: Teseda Corporation
• Inventors: Sanchez, Ralph, Akar, Armagan
• Granted Patent: US 9,659,136 B2
• Time in Patent Office: Days
• US Class Current: 716/106
• CPC Class Codes: G01R 27/28 Measuring attenuation, gain, phase shift or derived characteristics of electric four pole networks, i.e. two-port networks; Measuring transient response in line transmission systems H04B3/46
• CPC Class Codes: G01R 31/00 Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere measuring superconductive properties G01R33/1238; testing or measuring semiconductors or solid state devices during manufacture H01L22/00; testing line transmission systems H04B3/46
• CPC Class Codes: G01R 31/2803 by means of functional tests, e.g. logic-circuit-simulation or algorithms therefor testing electronic digital computers G06F11/00
• CPC Class Codes: G01R 31/281 Specific types of tests or tests for a specific type of fault, e.g. thermal mapping, shorts testing G01R31/2818 takes precedence
• CPC Class Codes: G06F 11/008 Reliability or availability analysis
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking
• CPC Class Codes: G06F 30/3308 using simulation
• CPC Class Codes: G06F 30/333 Design for testability [DFT], e.g. scan chain or built-in self-test [BIST]
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: G11C 29/56008 Error analysis, representation of errors

Abstract

Various embodiments related to identifying a candidate defect region in a semiconductor device are disclosed. For example, one embodiment includes receiving an electrical test mismatch reported for a scan chain; generating a physical representation of portion of a logical design of the semiconductor device, the physical representation including location information for physical instantiations of logical cells and logical interconnections included in the portion of the logical design; identifying a suspect logical region in the physical representation, the suspect logical region including a portion of the logical cells and the logical interconnections electrically connected with the scan chain; generating a candidate defect region within the semiconductor device, the candidate defect region being defined, via the physical representation, to include the physical instantiations of logical cells and logical interconnections included in the suspect logical region; and displaying the candidate defect region.

Claims

1. At a failure analysis computing device, a method for identifying a candidate defect region including a possible physical defect in a semiconductor device, the method comprising:

receiving an electrical test mismatch reported for a scan chain;

generating a physical representation of a portion of a logical design of the semiconductor device, the physical representation including location information for physical instantiations of logical cells and logical interconnections included in the portion of the logical design;

identifying a suspect logical region in the physical representation, the suspect logical region including a portion of the logical cells and the logical interconnections electrically connected with the scan chain;

generating the candidate defect region, the candidate defect region being defined, via the physical representation, to include the physical instantiations of the logical cells and the logical interconnections included in the suspect logical region; and

displaying the candidate defect region.

2. The method of claim 1, wherein receiving the electrical test mismatch comprises receiving a failure file including one or more of an electrical test pattern identifier for which the electrical test mismatch was reported, an observed electrical test value, an expected electrical test value, and a functional failure type identified by the electrical test mismatch.

3. The method of claim 2, wherein the failure file is formatted according to a standard test interface language (STIL).

4. The method of claim 1, wherein generating the physical representation includes:

receiving a logical design file comprising the portion of the logical design of the semiconductor device;

receiving a physical layout file comprising a portion of a physical layout of the semiconductor device; and

correlating logical cells included in the portion of the logical design with polygons included in portion of the physical layout.

5. The method of claim 4, wherein correlating the logical cells and the polygons includes comparing a logical cell instance name to a polygon instance name.

6. The method of claim 4, wherein one or more of the logical design file and the physical layout file is formatted according to one of an integrated circuit hardware description language and an electronic design automation language.

7. The method of claim 1, wherein the physical representation includes, for each logical cell, a polygon defining a physical region of the semiconductor device occupied by the physical instantiation of the logical cell.

8. The method of claim 7, wherein the candidate defect region includes the polygons for the logical cells included in the suspect logical region.

9. The method of claim 1, wherein identifying the suspect logical region comprises:

identifying a plurality of logic cones electrically connected with one or more failing scan cells of the scan chain; and

using the physical representation, identifying a physical region of the semiconductor device that includes physical instantiations of logical cells and interconnections of each of the plurality of logic cones; and

defining the suspect logical region as including overlapping physical regions of the plurality of logic cones.

10. The method of claim 9, further comprising adjusting a scope of the suspect logical region by eliminating from the suspect logical region those logic cones electrically connected with a failing scan cell exhibiting less than a predetermined scan cell failure frequency.

11. The method of claim 1, further comprising adjusting a scope of the suspect logical region in response to a user input to a graphical user interface, the graphical user interface configured to display one or more of the suspect logical region, the candidate defect region and a physical layout for the semiconductor device.

12. The method of claim 11, further comprising updating a display of the candidate defect region in response to the user input.

13. The method of claim 1, wherein displaying the candidate defect region comprises displaying one or more of a physical layout for the semiconductor device and the suspect logical region.

14. The method of claim 1, wherein displaying the candidate defect region comprises varying a display characteristic of one or more logical cells according to one or more of a scan cell mismatch frequency, a scan chain mismatch frequency, and a physical proximity of two or more logical cells.

15. At a failure analysis computing device, a method for identifying a candidate defect region including a possible physical defect in a semiconductor device, the method comprising:

receiving an electrical test mismatch reported for a scan chain;

generating a physical representation of a portion of a logical design of the semiconductor device, the physical representation comprising location information for physical instantiations of logical cells and logical interconnections included in the portion of the logical design;

identifying a plurality of logic cones electrically connected with one or more failing scan cells of the scan chain;

using the physical representation, identifying a physical region of the semiconductor device including physical instantiations of logical cells and logical interconnections of each of the plurality of logic cones;

defining the candidate defect region as including overlapping physical regions of the plurality of logic cones; and

displaying the candidate defect region.

16. The method of claim 15, wherein generating the physical representation includes:

receiving, for the portion of the logical design of the semiconductor device, a logical cell instance name for each logical cell included in the portion of the logical design;

receiving a portion of a physical layout of the semiconductor device including a polygon instance name for each polygon included in the portion of the physical layout; and

generating the location information for the physical instantiations of the logical cells by correlating the logical cell instance names with the polygon instance names.

17. A failure analysis computing device for identifying a candidate defect region including a possible physical defect in a semiconductor device, the computing device comprising:

a data-holding subsystem; and

a failure analysis module held by the data-holding subsystem and including instructions executable by a logic subsystem to;

receive an electrical test mismatch reported for a scan chain,

generate a physical representation of a portion of a logical design of the semiconductor device, the physical representation comprising location information for polygons, each polygon representing a physical instantiation of a logical cell or a logical interconnection included in the portion of the logical design,

identify a suspect logical region in the physical representation including logical cells and logical interconnections electrically connected with the scan chain,

generate the candidate defect region, the candidate defect region including the polygons for the logical cells included in the suspect logical region, and

display the candidate defect region.

18. The failure analysis computing device of claim 17, wherein the instructions are further executable to:

receive a failure file including the electrical test mismatch;

receive a logical cell instance name for each logical cell included in the portion of the logical design;

receive a portion of a physical layout of the semiconductor device including a polygon instance name for each polygon included in the portion of the physical layout; and

generate the location information for the physical instantiations of the logical cells by comparing the logical cell instance names with the polygon instance names.

19. The failure analysis computing device of claim 17, wherein the instructions are further executable to:

identify a plurality of logic cones electrically connected with one or more failing scan cells of the scan chain;

using the physical representation, identify a physical region of the semiconductor device including physical instantiations of logical cells and logical interconnections of each of the plurality of logic cones; and

define the suspect logical region as including overlapping physical regions of the plurality of logic cones.

20. The failure analysis computing device of claim 19, further comprising:

a display subsystem configured to display a graphical user interface showing one or more of the candidate defect region and the suspect logical region, wherein the instructions are further executable to;

adjust the scope of the suspect logical region in response to a user input to the graphical user interface, and

update the display of one or more of the candidate defect region and the suspect logical region responsive to the user input.