SUSPECT LOGICAL REGION SYNTHESIS FROM DEVICE DESIGN AND TEST INFORMATION
First Claim
1. At a failure analysis computing device, a method for identifying a candidate defect region including a possible physical defect in a semiconductor device, the method comprising:
- receiving an electrical test mismatch reported for a scan chain;
generating a physical representation of a portion of a logical design of the semiconductor device, the physical representation including location information for physical instantiations of logical cells and logical interconnections included in the portion of the logical design;
identifying a suspect logical region in the physical representation, the suspect logical region including a portion of the logical cells and the logical interconnections electrically connected with the scan chain;
generating the candidate defect region, the candidate defect region being defined, via the physical representation, to include the physical instantiations of the logical cells and the logical interconnections included in the suspect logical region; and
displaying the candidate defect region.
1 Assignment
0 Petitions
Accused Products
Abstract
Various embodiments related to identifying a candidate defect region in a semiconductor device are disclosed. For example, one embodiment includes receiving an electrical test mismatch reported for a scan chain; generating a physical representation of portion of a logical design of the semiconductor device, the physical representation including location information for physical instantiations of logical cells and logical interconnections included in the portion of the logical design; identifying a suspect logical region in the physical representation, the suspect logical region including a portion of the logical cells and the logical interconnections electrically connected with the scan chain; generating a candidate defect region within the semiconductor device, the candidate defect region being defined, via the physical representation, to include the physical instantiations of logical cells and logical interconnections included in the suspect logical region; and displaying the candidate defect region.
-
Citations
20 Claims
-
1. At a failure analysis computing device, a method for identifying a candidate defect region including a possible physical defect in a semiconductor device, the method comprising:
-
receiving an electrical test mismatch reported for a scan chain; generating a physical representation of a portion of a logical design of the semiconductor device, the physical representation including location information for physical instantiations of logical cells and logical interconnections included in the portion of the logical design; identifying a suspect logical region in the physical representation, the suspect logical region including a portion of the logical cells and the logical interconnections electrically connected with the scan chain; generating the candidate defect region, the candidate defect region being defined, via the physical representation, to include the physical instantiations of the logical cells and the logical interconnections included in the suspect logical region; and displaying the candidate defect region. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
-
-
15. At a failure analysis computing device, a method for identifying a candidate defect region including a possible physical defect in a semiconductor device, the method comprising:
-
receiving an electrical test mismatch reported for a scan chain; generating a physical representation of a portion of a logical design of the semiconductor device, the physical representation comprising location information for physical instantiations of logical cells and logical interconnections included in the portion of the logical design; identifying a plurality of logic cones electrically connected with one or more failing scan cells of the scan chain; using the physical representation, identifying a physical region of the semiconductor device including physical instantiations of logical cells and logical interconnections of each of the plurality of logic cones; defining the candidate defect region as including overlapping physical regions of the plurality of logic cones; and displaying the candidate defect region. - View Dependent Claims (16)
-
-
17. A failure analysis computing device for identifying a candidate defect region including a possible physical defect in a semiconductor device, the computing device comprising:
-
a data-holding subsystem; and a failure analysis module held by the data-holding subsystem and including instructions executable by a logic subsystem to; receive an electrical test mismatch reported for a scan chain, generate a physical representation of a portion of a logical design of the semiconductor device, the physical representation comprising location information for polygons, each polygon representing a physical instantiation of a logical cell or a logical interconnection included in the portion of the logical design, identify a suspect logical region in the physical representation including logical cells and logical interconnections electrically connected with the scan chain, generate the candidate defect region, the candidate defect region including the polygons for the logical cells included in the suspect logical region, and display the candidate defect region. - View Dependent Claims (18, 19, 20)
-
Specification