TRENCH MOSFET WITH SUPER PINCH-OFF REGIONS

• US 20120080748A1
• Filed: 09/30/2010
• Published: 04/05/2012
• Est. Priority Date: 09/30/2010
• Status: Abandoned Application

• Current Assignee: Force Mos Technology Co., Ltd.
• Original Assignee: Force Mos Technology Co., Ltd.
• Inventors: HSIEH, Fu-Yuan
• Application Number:
  US12/894,653
• Publication Number:
  US 20120080748A1
• Time in Patent Office: Days
• US Class Current: 257/331
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/086 Impurity concentration or distribution
• CPC Class Codes: H01L 29/0869 Shape cell layout H01L29/0696
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A trench MOSFET with short channel length and super pinch-off regions is disclosed, wherein the super pinch-off regions are implemented by forming at least two type pinch-off regions for punch-through prevention: a first type pinch-off region with a wide mesa width generated between lower portion of two adjacent trenched gates and below an anti-punch through region surrounding bottom of a trenched source-body contact filled with metal plug; a second type pinch-off region with a narrow mesa width generated below a body region and between upper portion of one trenched gate and the anti-punch-through region along sidewall of the trenched source-body contact.

Claims

1. A trench MOSFET with super pinch-off regions comprising:

a semiconductor chip comprising a substrate of a first conductivity doping type and an epitaxial layer of said first conductivity doping type, wherein said epitaxial layer formed onto top surface of said substrate and having lower doping concentration than said substrate;

a plurality of trenched gates extending from top surface of said semiconductor chip, said trenched gates filled with a conductive material insulated by a gate oxide layer from said semiconductor chip;

a source region of said first conductivity doping type located near top surface of a mesa which defined by an area between every two adjacent of said trenched gates;

a body region of a second conductivity doping type located in said mesa below said source region and adjacent to sidewall of said trenched gate;

a contact interlayer formed onto said top surface of said semiconductor chip;

a trenched source-body contact filled with a metal plug penetrating through said contact interlayer, said source region and said body region, and extending into said epitaxial layer in said mesa, wherein depth of said trenched source-body contact is shallower than bottom of said trenched gate;

an anti-punch through region of said second conductivity doping type wrapping around sidewall and bottom of said trenched source-body contact below a portion of said source region, wherein said anti-punch through region having higher doping concentration than said body region, and junction depth of said body region in said epitaxial layer is shallower than that of said anti-punch through region in a portion below bottom of said trenched source-body contact.

2. The trench MOSFET of claim 1, wherein said mesa width between every two adjacent of the trenched gates is less than 1.3 um.

3. The trench MOSFET of claim 1 further comprises a narrow mesa between sidewall of said anti-punch through region and adjacent said trenched gate having a mesa width less than 0.5 um.

4. The trench MOSFET of claim 1, wherein said source region has a doping concentration along a channel region same as that along said trenched source-body contact region at a same distance from top surface of said epitaxial layer, and junction depth of said source region along said channel region is same as along said trenched source-body contact.

5. The trench MOSFET of claim 1, wherein said source region has a doping concentration along a channel region lower than along said trenched source-body contact region at a same distance from top surface of said epitaxial layer, and junction depth of said source region along said channel region is shallower than that along said trenched source-body contact, and doping profile of said source region along said top surface of said epitaxial layer has a Gaussian-distribution from said trenched source-body contact to said channel region.

6. The trench MOSFET of claim 1, wherein said contact interlayer comprising a BPSG layer and an NSG layer beneath.

7. The trench MOSFET of claim 3, wherein said trenched source-body contact having greater trench width within said BPSG layer than within said NSG layer.

8. The trench MOSFET of claim 1, wherein said trenched source-body contact having vertical sidewall within said source region, said body region and said epitaxial layer.

9. The trench MOSFET of claim 1, wherein said trenched source-body contact having tapered sidewall within said source region, said body region and said epitaxial layer.

10. The trench MOSFET of claim 1, wherein said trenched source-body contact having vertical sidewall within said source region while having tapered sidewall within said body region and said epitaxial layer.

11. The trench MOSFET of claim 1, wherein said gate oxide is single gate oxide.

12. The trench MOSFET of claim 1, wherein said gate oxide is double gate oxide for Qgd reduction, each of said trenched gates includes an upper gate portion and a lower gate portion wherein said lower gate portion is surrounded with a lower gate oxide layer having a greater thickness than an upper gate oxide layer surrounding said upper gate portion, and said body region disposed above said lower gate portion of said trenched gate.

13. The trench MOSFET of claim 12, wherein the portion of said lower gate oxide layer having greater thickness is encompassed in said epitaxial layer and not reaching said substrate.

14. The trench MOSFET of claim 12, wherein the portion of said lower gate oxide layer having greater thickness penetrates into said substrate.

15. The trench MOSFET of claim 1, wherein said metal plug is tungsten plug padded by a barrier layer of Ti/TiN or Co/TiN or Ta/TiN.

16. The trench MOSFET of claim 1 further comprising a source metal padded by a resistance-reduction layer of Ti or Ti/TiN beneath which formed onto said contact interlayer and connecting to said metal plug.

17. The trench MOSFET of claim 1 further comprising a single implanted pinch-off island of said second conductivity doping type in said epitaxial layer underneath said anti-punch through region and between every two adjacent of said trenched gates.

18. The trench MOSFET of claim 1 further comprising multiple implanted pinch-off islands of said second conductivity doping type in said epitaxial layer underneath said anti-punch through region and between every two adjacent of said trenched gates.

19. The MOSFET of claim 1 further comprising an implanted pinch-off column region formed by multiple implanted pinch-off islands of said second conductivity doping type in said epitaxial layer underneath said anti-punch through region and between every two adjacent of said trenched gates.

20. The trench MOSFET of claim 1 further comprising a termination area comprising multiple floating trenched gates.

21. The trench MOSFET of claim 1, wherein said conductive material in said trenched gate is doped poly-silicon of said first conductivity doping type.

22. The trench MOSFET of claim 1, wherein said conductive material in said trenched gate is doped poly-silicon of said second conductivity doping type.

23. The trench MOSFET of claim 1, wherein said first conductivity doping type is N type, and said second conductivity type is P type.

24. The trench MOSFET of claim 1, wherein said first conductivity doping type is P type, and said second conductivity type is N type.

25. A method for manufacturing a trench MOSFET with super pinch-off regions comprising the steps of:

opening a plurality of gate trenches in an epitaxial layer of a first conductivity type which supported onto a substrate of said first conductivity type;

forming a gate oxide layer covering inner surface of said gate trenches and top surface of said epitaxial layer;

depositing doped poly-silicon layer onto said gate oxide layer and etching back to keep said doped poly-silicon within said gate trenches;

carrying out ion implantation of a second conductivity doping type dopant for formation of body region;

carrying out ion implantation of said first conductivity doping type dopant for formation of source region;

depositing a contact interlayer onto entire top surface;

applying a contact mask and carrying out dry oxide etching and dry silicon etching successively to open a contact trench between two adjacent of said gate trenches through said contact interlayer, said source region, said body region and into said epitaxial layer to form trenched source-body contact;

carrying out anti-punch through ion implantation of said second conductivity doping type dopant through said trenched source-body contact for formation of anti-punch through region surrounding bottom and sidewall of said contact trench below said source region.

26. The method of claim 25 further comprising a body diffusion step after body ion implantation.

27. The method of claim 25 further comprising applying a source mask before source ion implantation.

28. The method of claim 25 further comprising a source diffusion step after source ion implantation.

29. The method of claim 25 wherein said anti-punch through ion implantation is carried out with combination of zero degree ion implantation and angle ion implantation.

30. The method of claim 25 wherein said anti-punch through ion implantation is carried out with angle ion implantation.

31. The method of claim 25 further comprising additional zero degree ion implantation of said second conductivity doping type through said trenched source-body contact for formation of implanted pinch-off islands or column.

32. The method of claim 25 wherein said contact interlayer is combination of BPSG and NSG layers.

33. The method of claim 32 further comprising dilute HF dip step to enlarge contact CD of said contact trench in said BPSG layer.

34. The method of claim 25 further comprising the steps of:

carrying out RTA to activate dopant in said anti-PT region;

depositing a barrier layer of Ti/TiN or Co/TiN or Ta/TiN along inner surface of said trenched source-body contact and performing a step of RTA to form silicide;

depositing tungsten metal onto said barrier layer and etching back to form tungsten plug;

depositing a resistance reduction layer of Ti or Ti/TiN onto said BPSG layer and said tungsten plug;

depositing a front metal of Al alloys or Ni/Ag onto said resistance-reduction layer;

applying a metal mask to pattern said front metal and said resistance-reduction layer to form source metal;

grinding rear side of said substrate and depositing a back metal of Ti/Ni/Ag on rear side of said substrate to form drain electrode.