3D VIA CAPACITOR WITH A FLOATING CONDUCTIVE PLATE FOR IMPROVED RELIABILITY

• US 20120080771A1
• Filed: 10/05/2010
• Published: 04/05/2012
• Est. Priority Date: 10/05/2010
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Yang, Chih-Chao, Chen, Fen, Li, Baozhen
• Granted Patent: US 8,405,135 B2
• Time in Patent Office: Days
• US Class Current: 257/532
• CPC Class Codes: H01L 21/76805 the opening being a via or contact hole penetrating the underlying conductor
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06544 Design considerations for via connections, e.g. geometry or layout
• CPC Class Codes: H01L 2225/06565 the devices having the same size and there being no auxiliary carrier between the devices
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 28/91 made by depositing layers, e.g. by depositing alternating conductive and insulating layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The present invention provides a 3D via capacitor and a method for forming the same. The capacitor includes an insulating layer on a substrate. The insulating layer has a via having sidewalls and a bottom. A first electrode overlies the sidewalls and at least a portion of the bottom of the via. A first high-k dielectric material layer overlies the first electrode. A first conductive plate is over the first high-k dielectric material layer. A second high-k dielectric material layer overlies the first conductive plate and leaves a remaining portion of the via unfilled. A second electrode is formed in the remaining portion of the via. The first conductive plate is substantially parallel to the first electrode and is not in contact with the first and second electrodes. An array of such 3D via capacitors is also provided.

Claims

1. A capacitor, comprising:

an insulating layer on a substrate, said insulating layer including a via having sidewalls and a bottom;

a first electrode overlying said sidewalls and at least a portion of said bottom of said via;

a first high-k dielectric material layer overlying said first electrode;

a first conductive plate over said first high-k dielectric material layer;

a second high-k dielectric material layer formed to overlie the first conductive plate and to leave a remaining portion of said via unfilled; and

a second electrode formed in said remaining portion of said via, wherein said first conductive plate is substantially parallel to said first electrode and is not in contact with said first and second electrodes.

2. The capacitor of claim 1, further comprising a second conductive plate and a third high-k dielectric material layer between said second high-k dielectric material layer and said second electrode, wherein said second conductive plate is substantially parallel to said first electrode and is not in contact with said first and second electrodes and said first conductive plate.

3. The capacitor of claim 1, further comprising:

a lower interconnect level between said substrate and said insulating layer, said lower interconnect level including a first dielectric layer having a first conductive feature embedded therein; and

an upper interconnect level above said insulating layer, said upper interconnect level including a second dielectric layer having a second conductive feature embedded therein, wherein said first electrode is in contact with said second conductive feature and said second electrode is in contact with said first conductive feature.

4. The capacitor of claim 3, wherein said via has a via gouging extending partially through said first conductive feature and said via gouging is filled with said second electrode material.

5. The capacitor of claim 3, further comprising a first dielectric capping layer located between said lower interconnect level and said insulating layer.

6. The capacitor of claim 3, further comprising a second dielectric capping layer located between said upper interconnect level and said second electrode.

7. The capacitor of claim 3, further comprising a hardmask layer located between said upper interconnect level and said insulating layer.

8. The capacitor of claim 1, further comprising a barrier liner layer located between said first electrode and said insulating layer.

9. The capacitor of claim 1, wherein said first electrode has a first portion substantially perpendicular to said substrate and a second portion substantially parallel to said substrate.

10. The capacitor of claim 9, wherein the ratio of the height of said first portion to the length of said second portion is greater than 2.

11. The capacitor of claim 1, wherein said first electrode comprises Ta, Ru, Co, Pt, W, Rh, Ir, Au, Al, Ti, or an alloy of two or more of the foregoing materials.

12. The capacitor of claim 1, wherein said first and second high-k dielectric material layers are formed from a same dielectric material, said dielectric material comprises oxide-nitride-oxide, SiO₂, TaO₅, PSiN_x, Si₃N₄, SiON, SiC, TaO₂, ZrO₂, HfO₂, HfSiO₂, Al₂O₃, or any combination of two or more of the foregoing materials.

13. The capacitor of claim 12, wherein said dielectric material has a dielectric constant in the range from about 5 to about 60.

14. The capacitor of claim 1, wherein said second electrode comprises Cu, Al, W, Ru, Rh, Ir, Co, or an alloy comprising two or more of the foregoing metals.

15. The capacitor of claim 1, wherein said first conductive plate comprises Ta, Ru, Co, Pt, W, Rh, Ir, Au, Al, Ti, or an alloy of two or more of the foregoing materials.

16. An array of capacitors, comprising a second chip having a second capacitor bonded atop a first chip having a first capacitor, said first and second capacitors having substantially the same structure and each comprising:

an insulating layer on a substrate, said insulating layer including a via having sidewalls and a bottom;

a first electrode overlying said sidewalls and at least a portion of said bottom of said via;

a first high-k dielectric material layer overlying said first electrode;

a first conductive plate over said first high-k dielectric material layer;

a second high-k dielectric material layer formed to overlie the first conductive plate and to leave a remaining portion of said via unfilled;

a second electrode formed in said remaining portion of said via, wherein said first conductive plate is substantially parallel to said first electrode and is not in contact with said first and second electrodes;

a lower interconnect level between said substrate and said insulating layer, said lower interconnect level including a first dielectric layer having a first conductive feature embedded therein; and

an upper interconnect level above said insulating layer, said upper interconnect level including a second dielectric layer having a second conductive feature embedded therein, wherein said first electrode is in contact with said second conductive feature and said second electrode is in contact with said first conductive feature; and

wherein said first conductive feature of said second capacitor is in contact with said second conductive feature of said first capacitor, and said second conductive feature of said second capacitor is connected to said first conductive feature of said first capacitor through a conductor.

17. The array of claim 16, further comprising a third chip having a third capacitor bonded atop said second chip, wherein said third capacitor has substantially the same structure as said first and second capacitors, said first conductive feature of said third capacitor is in contact with said second conductive feature of said second capacitor, and said second conductive feature of said third capacitor is connected to said first conductive feature of said second capacitor through a second conductor.

18. A method of forming a capacitor, comprising:

providing a substrate having a lower interconnect level including a first dielectric layer having a first conductive feature embedded therein, a first dielectric capping layer on said lower interconnect level, an insulating layer on said first dielectric capping layer, and a patterned hardmask layer having a top surface on said insulating layer, wherein said insulating layer has a via that extends partially through said first dielectric capping layer, said via having sidewalls and a bottom;

forming a first electrode layer over said sidewalls and said bottom of said via and said top surface of said hardmask layer;

forming a first high-k dielectric material layer over said first electrode layer;

forming a first conductive plate layer over said first high-k dielectric material layer;

forming a via gouging at said bottom of said via by removing a portion of said first conductive plate layer, a portion of said first high-k dielectric material layer, a portion of said first electrode layer, a portion of said first dielectric capping layer and a portion of said first conductive feature, said via gouging having sidewalls and a bottom and extending partially through said first conductive feature;

forming a second high-k dielectric material layer over said first conductive plate layer and over said sidewalls and said bottom of said via gouging;

selectively removing said second high-k dielectric material layer at said bottom and lower sidewalls of said via gouging;

filling said via and said via gouging with a second electrode material;

partially removing said second electrode material to form a recess at said top of said via;

forming a second dielectric capping layer in said recess; and

forming an upper interconnect level including a second dielectric layer having a second conductive feature embedded therein over said insulating layer, wherein second conductive feature is in contact with said first conductive plate layer.

19. The method of claim 18, wherein said providing said substrate comprises:

forming said first conductive feature in said first dielectric layer to form said lower interconnect level;

forming said first dielectric capping layer on said lower interconnect level;

forming said insulating layer on said first dielectric capping layer;

forming a patterned hardmask layer having a via pattern on said insulating layer; and

transferring said via pattern into said insulating layer and partially into said first dielectric capping layer.

20. The method of claim 18, further comprising, before said forming said first electrode layer, forming a barrier liner layer over said sidewalls and said bottom of said via and said top surface of said hardmask layer.

21. The method of claim 18, wherein said forming said via gouging comprises directional sputtering with a gas source.

22. The method of claim 21, wherein said gas source comprises Ar, He, Xe, Ne, Kr, Rn, N₂, NH₃, or H₂.

23. The method of claim 18, wherein said forming said first electrode layer comprises a physical vapor deposition (PVD), a chemical vapor deposition (CVD), a plasma enhanced chemical vapor deposition (PECVD), an atomic layer deposition (ALD) process, or a plasma enhanced atomic layer deposition (PEALD).

24. The method of claim 23, wherein said first electrode layer comprises Ta, Ru, Co, Pt, W, Rh, Ir, Au, Al, Ti, or an alloy of two or more of the foregoing materials.

25. The method of claim 18, wherein said forming said first high-k dielectric material layer and said forming said second high-k dielectric material layer comprises a chemical vapor deposition (CVD), a plasma enhanced chemical vapor deposition (PECVD), an atomic layer deposition (ALD) process, or a plasma enhanced atomic layer deposition (PEALD).

26. The method of claim 25, wherein said first high-k dielectric material layer and said second high-k dielectric material layer are formed from a same dielectric material, said dielectric material comprises oxide-nitride-oxide, SiO₂, TaO₅, PSiN_x, Si₃N₄, SiON, SiC, TaO₂, ZrO₂, HfO₂, Al₂O₃, or any combination of two or more of the foregoing materials.

27. The method of claim 18, wherein said forming said first conductive plate layer comprises a physical vapor deposition (PVD), a chemical vapor deposition (CVD), a plasma enhanced chemical vapor deposition (PECVD), an atomic layer deposition (ALD) process, or a plasma enhanced atomic layer deposition (PEALD).

28. The method of claim 27, wherein said first conductive plate layer comprises Ta, Ru, Co, Pt, W, Rh, Ir, Au, Al, Ti, or an alloy of two or more of the foregoing materials.

29. The method of claim 18, wherein said forming filling said via and said via gouging with said second electrode material comprises chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), sputtering, chemical solution deposition or plating.

30. The method of claim 29, wherein said second electrode material comprises Cu, Al, W, Ru, Rh, Ir, Co, or an alloy comprising two or more of the foregoing metals.

31. The method of claim 18, wherein said partially removing said second electrode material comprises a wet etching process.

32. The method of claim 31, wherein said wet etching process is performed using a chemical comprising HF, HCl, H₂SO₄, or any combination of two or more of said foregoing materials.