METHOD OF DRIVING DISPLAY PANEL AND DISPLAY APPARATUS FOR PERFORMING THE SAME

• US 20120081410A1
• Filed: 05/03/2011
• Published: 04/05/2012
• Est. Priority Date: 09/30/2010
• Status: Abandoned Application

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: Yeo, Dong-Hyun, Jeon, Byung-Kil, Yoo, Byoung-Seok, Kim, Yong-Bum, Jeon, Jae-Gwan
• Application Number:
  US13/099,629
• Publication Number:
  US 20120081410A1
• Time in Patent Office: Days
• US Class Current: 345/690
• CPC Class Codes: G09G 2300/0426 Layout of electrodes and connections
• CPC Class Codes: G09G 2320/0223 Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
• CPC Class Codes: G09G 3/2092 Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto suitable for both CRT and flat panel G09G5/003; specific for a CRT G09G1/165
• CPC Class Codes: G09G 3/3685 Details of drivers for data electrodes

Abstract

Rather than using complex zigzag patterns or the like for counter-compensating for the different lengths of fanout lines used to transmit data line drive voltages from more concentrated source points of the drive voltages to more spread apart data lines of a given display panel, digital data signals that represent the to be output data line drive voltages are automatically adjusted so that the data line drive voltages output from the concentrated source points are pre-adjusted to counter voltage drop difference effects that will be applied to those pre-adjusted data line drive voltages by the difference of resistances among the fanout lines of different lengths.

Claims

1. A method of driving a display panel that has differing fanout lines coupling respective drive voltage outputting channels disposed at near and close together ends of the fanout lines to corresponding ends of respective data lines where the data line ends are disposed at distal and further spaced apart ends of the fanout lines, the method comprising:

receiving an initial image-representing digital data signal and automatically generating therefrom a corresponding, compensated digital data signal that counter-compensate for a difference of developed voltage that would otherwise appear at the distal end of a corresponding fanout line in response to a predetermined drive voltage presented at the voltage outputting channel of that corresponding fanout line, where the difference of developed voltage is due to a difference of resistance in the corresponding fanout line relative to a different resistance of at least one differing other one of the fanout lines; and

respectively outputting an analog data voltage corresponding to the compensated digital data signal from a respective one of the drive voltage outputting channels for thereby transmitting the output analog data voltage through the corresponding fanout line to thus drive a corresponding one of the data lines.

2. The method of claim 1 wherein:

the generating of the corresponding, compensated digital data signal includes receiving an initial grayscale digital data signal representing a corresponding grayscale and digitally multiplying the received initial grayscale digital data signal by a selected fanout compensating value to thus generate the corresponding, compensated digital data signal, and

where the selected fanout compensating value is selected from a plurality of stored fanout compensating values respectively corresponding to fanout lines of the display that have relatively large resistances and to fanout lines of the display that have relatively smaller resistances.

3. The method of claim 2, wherein the fanout compensating value is inversely proportional to a light transmittance reduction value of a pixel connected to the data line of the corresponding output channel, where the light transmittance reduction value is a percentage of light transmittance ability lost due to the difference of developed voltage.

4. The method of claim 2, wherein the generating of the corresponding, compensated digital data signal comprises:

receiving an external R, G or B input image data signal;

automatically determining a fanout line corresponding to the received R, G or B input image data signal;

automatically determining the fanout compensating value corresponding to the determined fanout line; and

automatically applying the determined fanout compensating value to a grayscale value of the received R, G or B input image data signal to thereby produce a corresponding compensated R, G or B image data signal.

5. The method of claim 4, wherein the fanout compensating value is determined using a lookup table storing the plurality of fanout compensating values.

6. The method of claim 5, wherein the lookup table stores one base fanout compensating value for a plurality of the fanout lines,

the base fanout compensating value for a given fanout line is determined based on the lookup table, and

linear interpolation is used to produce from the base fanout compensating value, a refined fanout compensating value of a fanout line whose refined fanout compensating value is not stored in the lookup table.

7. The method of claim 2, wherein the compensated data increases the data voltages outputted to the fanout lines except for the shortest fanout line with respect to the data voltage outputted to the shortest fanout line.

8. The method of claim 2, wherein the compensated data decreases the data voltages outputted to the fanout lines except for the longest fanout line with respect to the data voltage outputted to the longest fanout line.

9. The method of claim 2, wherein the compensated data decreases the data voltages outputted to the fanout lines shorter than a first predetermined length with respect to the data voltage outputted to a fanout line having the first length, and

the compensated data increases the data voltages outputted to the fanout lines longer than the first predetermined length with respect to the data voltage outputted to the fanout line having the first length.

10. A display apparatus comprising:

a display panel comprising a plurality of data lines spaced apart at a first pitch dimension;

a driving chip having a plurality of output terminals for outputting a corresponding plurality of data voltages to the data lines, where the chip output terminals are spaced apart by a dimension smaller than the first pitch dimension of the data lines;

a fanout part having a plurality of fanout lines of differing resistances, the fanout lines providing interconnection between corresponding ones of the chip output terminals and the data lines; and

a timing controller structured to generate compensated digital data signals that electronically compensate for differences of resistances amongst the differing fanout lines so that analog voltages delivered to respective ones of the data lines are not varied as a result of the differing resistances of the fanout lines.

11. The display apparatus of claim 10, wherein the timing controller includes a grayscale data adjusting part that automatically applies selected fanout compensating values to corresponding grayscale representing data signals to thereby generate the compensated digital data signals.

12. The display apparatus of claim 11, wherein the fanout compensating value is inversely proportional to a light transmittance of a pixel connected to the data line.

13. The display apparatus of claim 11, wherein the selected fanout compensating values are stored in a lookup table of the display apparatus.

14. The display apparatus of claim 13, wherein the lookup table stores the fanout compensating values corresponding to a part of the fanout lines, and

the timing controller automatically determines the fanout compensating value for the fanout line stored in the lookup table based on the lookup table and the fanout compensating value for the fanout line, which is not stored in the lookup table, using a linear interpolation.

15. The display apparatus of claim 13, further comprising a memory storing the lookup table.

16. The display apparatus of claim 11, wherein the timing controller generates the compensated data in a way that increases the data voltages outputted to the fanout lines except for the shortest fanout line with respect to the data voltage outputted to the shortest fanout line.

17. The display apparatus of claim 11, wherein the timing controller generates the compensated data in a way that decreases the data voltages outputted to the fanout lines except for the longest fanout line with respect to the data voltage outputted to the longest fanout line.

18. The display apparatus of claim 11, wherein the timing controller generates the compensated data to decrease the data voltages outputted to the fanout lines shorter than a first length with respect to the data voltage outputted to a fanout line having the first length, and to increase the data voltages outputted to the fanout lines longer than the first length with respect to the data voltage outputted to the fanout line having the first length.