LOW VOLTAGE PROGRAMMING IN NAND FLASH

• US 20120081962A1
• Filed: 10/06/2010
• Published: 04/05/2012
• Est. Priority Date: 09/30/2010
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Huang, Jyun-Siang, Tsai, Wen-Jer, Tsai, Ping-Hung
• Granted Patent: US 8,947,939 B2
• Time in Patent Office: Days
• US Class Current: 365/185.15
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written

Abstract

A memory device includes a plurality of memory cells arranged in series in the semiconductor body, such as a NAND string, having a plurality of word lines. A selected memory cell is programmed by hot carrier injection. The program operation is based on metering a flow of carriers between a first semiconductor body region on a first side of the selected cell in the NAND string and a second semiconductor body region on a second side of the selected cell. A program potential higher than a hot carrier injection barrier level is applied to the selected cell, and then the drain to source voltage across the selected cell and the flow of carriers in the selected cell reach a level sufficient to support hot carrier injection, which is controlled by a switch cell adjacent the selected cell.

Claims

1. A memory comprising:

a plurality of memory cells arranged in series in a semiconductor body;

a plurality of word lines, word lines in the plurality coupled to corresponding memory cells in the plurality of memory cells; and

control circuitry coupled to the plurality of word lines adapted for programming a selected memory cell in the plurality of memory cells corresponding to a selected word line by;

biasing one of first and second ends of the plurality of memory cells to a drain side voltage, and another of the first and second ends to a source side voltage during the program interval,

applying drain-side pass voltages to word lines between the selected word line and said one of first and second ends during a program interval,

applying source-side pass voltages to word lines between the selected word line and said other of first and second ends during a program interval,

applying a program voltage to the selected word line during the program interval, and

applying a switching voltage to a word line and corresponding memory cell adjacent the selected word line and selected memory cell to control conductance during the program interval.

2. The memory of claim 1, wherein the switching voltage varies during the program interval, so that during a portion of the program interval hot carrier injection occurs in the selected memory cell to set the selected memory cell to a program threshold level.

3. The memory of claim 1, wherein said applying a switching voltage comprises an iteration including a sequence of pulses of increasing or decreasing magnitude.

4. The memory of claim 1, wherein said applying a switching voltage comprises applying one or more pulses having at least one of a ramped rising and ramped falling edge.

5. The memory of claim 1, wherein the plurality of memory cells is arranged as a NAND string.

6. The memory of claim 1, including a first switch between a reference line and the first end of the plurality of memory cells and a second switch between a first bit line and the second end of the plurality of memory cells, and wherein the control circuitry turns on the first switch during the program interval, and turns on the second switch during the program interval.

7. The memory of claim 6, including a second plurality of memory cells coupled to the plurality of word lines, a corresponding first switch between said reference line and a first end of the second plurality of memory cells and a corresponding second switch between a second bit line and a second end of the second plurality of memory cells, and wherein the control circuitry applies the drain side voltage via said first bit line to the second end of the plurality of memory cells, applies the source side voltage via the reference line to the first end of the plurality of memory cells, and applies a voltage equal to or near the source side voltage via the second bit line to the second end of the second plurality of memory cells to inhibit hot carrier injection.

8. The memory of claim 6, including a second plurality of memory cells coupled to the plurality of word lines, a corresponding first switch between said reference line and a first end of the second plurality of memory cells and a corresponding second switch between a second bit line and a second end of the second plurality of memory cells, and wherein the control circuitry applies the source side voltage via said first bit line to the second end of the plurality of memory cells, applies the drain side voltage via the reference line to the first end of the plurality of memory cells, and applies a voltage equal to or near the drain side voltage via the second bit line to the second end of the second plurality of memory cells to inhibit hot carrier injection.

9. The memory of claim 6, including a second plurality of memory cells coupled to the plurality of word lines and a second bit line, and wherein the control circuitry applies a voltage to the second bit line to inhibit hot carrier injection.

10. The memory of claim 6, including an additional cell in series with the plurality of memory cells in the semiconductor body and an additional word line, and disposed between the plurality of memory cells and one of the first switch and the second switch, and wherein the control circuitry applies the switching voltage to the additional word line during the program interval for a target cell adjacent the additional word line.

11. The memory of claim 1, including a first switch between a reference line and a first end of the plurality of memory cells and a second switch between a bit line and a second end of the plurality of memory cells.

12. The memory of claim 11, including a second plurality of memory cells coupled to the plurality of word lines and to a second bit line, and wherein the control circuitry operates during the program interval to bias the second bit line so that a first semiconductor body region for the second plurality of cells on a first side of the selected word line and a second semiconductor body region for the second plurality of cells on a second side of the selected word line are biased near to a given voltage level, such as the source side voltage or the drain side voltage, to inhibit hot carrier generation.

13. The memory of claim 1, including a plurality of bit lines and a plurality of common source lines, wherein the plurality of memory cells is arranged as a first NAND string coupled to a first bit line in the plurality of bit lines and a first common source line in the plurality of common source lines, and including

a plurality of additional NAND strings coupled to the plurality of word lines, the plurality of bit lines, and the plurality of common source lines, wherein a second NAND string in the plurality of additional NAND strings is coupled to the first bit line and to a second common source line in the plurality of common source lines.

14. The memory of claim 13, wherein the first and second NAND strings are arranged adjacent to one another in a row direction.

15. The memory of claim 13, wherein the first and second NAND strings are arranged adjacent to one another in a column direction.

16. The memory of claim 1, including a plurality of layers of memory cells, plurality of bit lines and a plurality of common source lines, wherein the plurality of memory cells is arranged as a first NAND string in one layer of the plurality of layers coupled to a first bit line in the plurality of bit lines and a first common source line in the plurality of common source lines, and including

a plurality of additional NAND strings coupled to the plurality of word lines, the plurality of bit lines, and the plurality of common source lines, wherein a second NAND string in the plurality of additional NAND strings and in another layer in the plurality of layers is coupled to the first bit line and to a second common source line in the plurality of common source lines and a third NAND string in the plurality of additional NAND strings and in said one layer in the plurality of layers is coupled to another bit line and to said first common source line.

17. The memory of claim 1, wherein the control circuitry applies switching voltages to more than one word line during the program interval.

18. The memory of claim 1, wherein the plurality of memory cells is arranged as a NAND string in a common source NAND flash memory array.

19. The memory of claim 1, wherein the plurality of memory cells is arranged as a NAND string in a virtual ground NAND flash memory array.

20. A memory comprising:

a NAND string including a plurality of memory cells arranged in series in a semiconductor body;

a plurality of word lines, word lines in the plurality coupled to corresponding memory cells in the plurality of memory cells; and

control circuitry coupled to the plurality of word lines adapted for programming a selected memory cell in the plurality of memory cells corresponding to a selected word line by;

controlling conductance in the NAND string by applying a switching voltage to a word line adjacent the selected word line to induce an effective source in a first semiconductor body region on one side of a selected cell and to induce an effective drain in a second semiconductor body region on another side of the selected cell in the NAND string;

biasing the first semiconductor body region to a source side voltage;

biasing the second semiconductor body region to a drain side voltage; and

applying a program potential greater than a hot carrier injection barrier level to the selected cell.

21. A method for inducing hot carrier injection in a selected cell in a NAND string in a NAND array, comprising:

controlling conductance in the NAND string by applying a switching voltage to a word line adjacent the selected word line to induce an effective source on a first side of a selected cell and to induce an effective drain on a second side of the selected cell in the NAND string;

biasing the effective drain to a drain side voltage;

biasing the effective source to a source side reference voltage;

applying a program potential greater than a hot carrier injection barrier level to the selected cell.

22. The method of claim 21, wherein NAND strings in the NAND array include a first switch between a first end of the NAND string and a bit line or reference line and a second switch between a second end of the NAND string and a bit line or reference line, and wherein said biasing includes:

turning on the first switch in the NAND string including the selected cell and applying the source side voltage to the first end of the NAND string via the first switch; and

turning on the second switch in the NAND string including the selected cell and applying the drain side voltage to the second end of the NAND string via the second switch.

23. The method of claim 21, wherein NAND strings in the NAND array include a first switch between a first end of the NAND string and a bit line or reference line and a second switch between a second end of the NAND string and a bit line or reference line, and wherein said biasing includes:

turning on the first switch in the NAND string including the selected cell and applying the drain side voltage to the first end of the NAND string via the first switch; and

turning on the second switch in the NAND string including the selected cell and applying the source side voltage to the second end of the NAND string via the second switch.

24. The method of claim 23, including turning off one of the first and second switches in at least one unselected NAND string.

25. The method of claim 23, including turning on the first and second switches in at least one unselected NAND string.