SHIFT REGISTER
First Claim
1. A shift register supported by an insulative substrate, wherein:
- the shift register includes a plurality of stages each sequentially outputting output signals from an output terminal;
each of the plurality of stages includes a first transistor for pulling up a potential of the output terminal, a plurality of second transistors whose source region or drain region is electrically connected to a gate electrode of the first transistor, and at least one third transistor receiving a clock signal supplied to a gate electrode thereof; and
the at least one third transistor includes a multi-channel transistor having an active layer including at least two channel regions, a source region and a drain region.
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Accused Products
Abstract
A shift register of the present invention is a shift register supported by an insulative substrate, wherein: the shift register includes a plurality of stages each sequentially outputting output signals from an output terminal; each of the plurality of stages includes a first transistor (MA) for pulling up a potential of the output terminal, a plurality of second transistors (ME and MF) whose source region or drain region is electrically connected to a gate electrode of the first transistor (MA), and at least one third transistor (MCd) receiving a clock signal supplied to a gate electrode thereof; and the at least one third transistor (MCd) includes a multi-channel transistor (MCd) having an active layer including at least two channel regions, a source region and a drain region. This improves characteristics of a shift register forming a monolithic gate driver.
39 Citations
15 Claims
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1. A shift register supported by an insulative substrate, wherein:
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the shift register includes a plurality of stages each sequentially outputting output signals from an output terminal; each of the plurality of stages includes a first transistor for pulling up a potential of the output terminal, a plurality of second transistors whose source region or drain region is electrically connected to a gate electrode of the first transistor, and at least one third transistor receiving a clock signal supplied to a gate electrode thereof; and the at least one third transistor includes a multi-channel transistor having an active layer including at least two channel regions, a source region and a drain region. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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Specification