DIE EXPANSION BUS

• US 20120084483A1
• Filed: 09/29/2011
• Published: 04/05/2012
• Est. Priority Date: 09/30/2010
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Sanjive, Agarwala
• Granted Patent: US 8,549,463 B2
• Time in Patent Office: Days
• US Class Current: 710/305
• CPC Class Codes: G06F 13/14 Handling requests for interconnection or transfer
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A die expansion bus efficiently couples a supplemental portion of a processing system to an original portion of the processing system on a die. The die expansion bus couples bus subsystems of the supplemental portion of the processing system to the bus subsystems of the original portion of the processing system. The original portion of the processing system is arranged to control the data resources of the supplemental portion of the processing system by accessing the memory endpoints associated with the bus subsystems of the supplemental portion of the processing system.

Claims

1. A method for updating processing system designs on integrated circuits, comprising:

arranging an original portion of a processing system in a substrate in accordance with a substantially fixed layout of the original portion of the processing system, wherein the original portion of the processing system includes data resources for processing data and includes bus subsystems having memory endpoints for controlling the data resources of the original portion of the processing system;

arranging a supplemental portion of the processing system in the substrate in accordance with a layout of the supplemental portion of the processing system, wherein the supplemental portion of the processing system includes data resources for processing data and includes bus subsystems having memory endpoints for controlling the data resources of the supplemental portion of the processing system, and wherein the layout of the supplemental portion of the processing system is generated after the layout of the original portion of the processing system has been substantially fixed; and

arranging a die expansion bus in the substrate wherein the die expansion bus is arranged to couple the bus subsystems of the supplemental portion of the processing system to the bus subsystems of the original portion of the processing system, and wherein the original portion of the processing system is arranged to control the data resources of the supplemental portion of the processing system by accessing the memory endpoints associated with the bus subsystems of the supplemental portion of the processing system.

2. The method of claim 1, wherein the substantially fixed layout is provided as a standard cell for integrated circuit design.

3. The method of claim 1, wherein the bus subsystem is a clocking system that provides memory endpoints for selecting clock signals.

4. The method of claim 1, wherein the bus subsystem is a power management system that provides memory endpoints for applying various levels of system power to selected resources.

5. The method of claim 1, wherein the bus subsystem is a verification system that provides memory endpoints for providing test stimulus to and reading test results from the selected resources.

6. The method of claim 1, comprising arranging a plurality of die expansion busses around the periphery of the original portion of the processing system, wherein the plurality of die expansion busses are arranged to couple bus subsystems of a plurality of supplemental portions of the processing system to the bus subsystems of the original portion of the processing system.

7. The method of claim 6, comprising arranging the plurality of supplemental portions of the processing system around the periphery of the original portion of the processing system and adjacent to an associated die expansion bus.

8. The method of claim 1, comprising coupling the supplemental portion of the processing system that is located on a first die of a die stack to the original portion of the processing system that is on a second die of the die stack using through-silicon-vias (TSVs).

9. The method of claim 8, comprising queuing pending events for transferring data across a bus switch fabric of the original portion of the processing system and a bus switch fabric of the supplemental original portion of the processing system.

10. The method of claim 9, using a cross-domain bridge to couple the bus switch fabric of the original portion of the processing system to the bus switch fabric of the supplemental original portion.

12. The method of claim 1, comprising generating a clock in the original portion of the processing system, dividing the clock in the die expansion bus, and receiving the divided clock in the supplemental portion of the processing system.

11. The method of claim 11, comprising transferring data asynchronously across the cross-domain bridge.

13. A system on chip, comprising:

an original portion of a processing system that is arranged in a substrate in accordance with a substantially fixed layout of the original portion of the processing system, wherein the original portion of the processing system includes data resources for processing data and includes bus subsystems having memory endpoints for controlling the data resources of the original portion of the processing system;

a supplemental portion of the processing system that is arranged in the substrate in accordance with a layout of the supplemental portion of the processing system, and wherein the supplemental portion of the processing system includes data resources for processing data and includes bus subsystems having memory endpoints for controlling the data resources of the supplemental portion of the processing system; and

a die expansion bus that is arranged in the substrate, wherein the die expansion bus is arranged to couple the bus subsystems of the supplemental portion of the processing system to the bus subsystems of the original portion of the processing system, and wherein the original portion of the processing system is arranged to control the data resources of the supplemental portion of the processing system by accessing the memory endpoints associated with the bus subsystems of the supplemental portion of the processing system.

14. The system of claim 13, wherein the layout of the supplemental portion of the processing system is arranged in the periphery of the substrate.

15. The system of claim 13, wherein the supplemental portion of the processing system is located on a first die of a die stack and is coupled to the original portion of the processing system that is on a second die of the die stack.

16. The system of claim 13, wherein the supplemental portion of the processing system is located on a first die of a die stack and is coupled to the original portion of the processing system that is on a second die of the die stack using through-silicon-vias (TSVs).

17. The system of claim 16, wherein communications between the first die of the die stack and the second die of the die stack proceed at a clock rate at which a processor of the processing system operates.

18. A memory-mapped system for updating processing system designs on integrated circuits, comprising:

original bus subsystems having memory endpoints for controlling data resources of an original portion of the processing system, wherein the original portion is arranged in a central portion of a die in which the processing system is arranged;

supplemental bus subsystems having memory endpoints for controlling data resources of a supplemental portion of the processing system, wherein the supplemental portion is arranged in the peripheral portion of the die in which the processing system is arranged; and

a die expansion bus that is arranged to couple the memory endpoints of the supplemental bus subsystems to original portion of the processing system, wherein the original portion controls the supplemental bus subsystems using the memory endpoints of the supplemental bus subsystems.

19. The memory-mapped system of claim 18, wherein the memory-mapped endpoints are control registers for controlling a corresponding bus subsystem.

20. The memory-mapped system of claim 19, wherein the bus subsystems of the supplemental portion of the processing system includes at least two of a clock subsystem, a test subsystem, and a power management subsystem.