STORAGE SYSTEM LOGICAL BLOCK ADDRESS DE-ALLOCATION MANAGEMENT AND DATA HARDENING

• US 20120084492A1
• Filed: 03/27/2010
• Published: 04/05/2012
• Est. Priority Date: 03/27/2009
• Status: Active Grant

• Current Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Original Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Inventors: Stenfort, Ross
• Granted Patent: US 8,671,258 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 1/30 Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations for resetting only G06F1/24
• CPC Class Codes: G06F 1/3234 Power saving characterised by the action undertaken
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/14 Protection against unauthorised use of memory or access to memory
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2213/0038 System on Chip
• CPC Class Codes: G06F 3/0605 by facilitating the interaction with a user or administrator
• CPC Class Codes: G06F 3/0661 Format or protocol conversion arrangements
• CPC Class Codes: G06F 3/0689 Disk arrays, e.g. RAID, JBOD
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 5/141 Battery and back-up supplies

Abstract

Storage system Logical Block Address (LBA) de-allocation management and data hardening provide improvements in performance, efficiency, and utility of use. Optionally, LBA de-allocation information in a first format (e.g. associated with a first protocol) is converted to a second format (e.g. associated with a second protocol). An example of the first protocol is a Small Computer System Interface (SCSI) protocol, and an example of the second protocol is an Advanced Technology Attachment (ATA) protocol. Optionally, LBA de-allocation status information is determined by a storage device, such as a Solid-State Disk (SSD), and communicated to another device such as an initiator, expander, or bridge. Optionally, data stored on an SSD is hardened, such as in response to determining that the SSD is to be powered off. The hardening is via power supplied by an energy storage element, such as a super capacitor or a battery.

Claims

1. A system, comprising:

a first I/O interface enabled to receive first storage protocol commands;

a second I/O interface enabled to output second storage protocol commands;

a conversion unit enabled to convert at least some of the received first storage protocol commands into the second storage protocol commands; and

wherein a first storage protocol de-allocation command of the first storage protocol commands is received in a first format by the first I/O interface and is converted and output in a second format as a second storage protocol de-allocation command of the second storage protocol commands.

2. The system of claim 1, wherein the storage protocol de-allocation commands are logical block de-allocation commands comprising at least one logical block address.

3. The system of claim 1, further comprising mass storage responsive to the second storage protocol commands.

4. The system of claim 3, wherein the second storage protocol de-allocation command requests de-allocation, with respect to at least one logical block address, of a selected one of user data and protection data, and the mass storage conditionally fulfills the request whenever the user data and the protection data can be de-allocated independently.

5. The system of claim 3, further comprising an initiator of the first storage protocol commands.

6. The system of claim 5, further comprising an expander.

7. The system of claim 3, wherein the first I/O interface, the second I/O interface, and the conversion unit are implemented as a unified assembly.

8. The system of claim 7, wherein the unified assembly is a bridge unit enabled to couple with an initiator unit generating the first storage protocol commands and the bridge unit is further enabled to couple with a mass storage unit responsive to the second storage protocol commands.

9. The system of claim 7, wherein in response to at least one instance of power-specific information received by the first I/O interface of the bridge unit, the second I/O interface of the bridge unit outputs a power-specific command, and the mass storage unit response to the power-specific command comprises hardening data.

10. The system of claim 3, wherein the mass storage unit is implemented using flash memory.

11. The system of claim 3, wherein the mass storage unit is a solid-state drive.

12. The system of claim 1, wherein the first storage protocol commands are compatible with SCSI protocol commands and the second storage protocol commands are compatible with ATA protocol commands.

13. The system of claim 12, wherein the first storage protocol de-allocation command is a SCSI UNMAP command and the second storage protocol de-allocation command is an ATA data set management command.

14. The system of claim 12, wherein the first storage protocol de-allocation command is a command to write a pattern of data.

15. The system of claim 14, wherein the command to write a pattern of data is a selected one of a WRITE SAME command and a FORMAT command.

16. The system of claim 14, wherein the pattern of data is in accordance with a predetermined criteria.

17. The system of claim 1, wherein the first storage protocol commands are compatible with SAS protocol commands and the second storage protocol commands are compatible with SATA protocol commands.

18. The system of claim 3, wherein the mass storage is implemented using flash memory.

19. The system of claim 3, wherein the mass storage is a solid-state drive.

20. The system of claim 3, wherein the first I/O interface, the second I/O interface, the conversion unit, and the mass storage are implemented as a unified assembly.

21. The system of claim 20, wherein the unified assembly is a drive unit enabled to couple with an initiator unit generating the first storage protocol commands.

22. The system of claim 21, wherein the mass storage is implemented using flash memory.

23. The system of claim 21, wherein the conversion unit is implemented at least partially with dedicated logic.

24. The system of claim 21, wherein the conversion unit comprises at least one dedicated memory buffer.

25. The system of claim 21, wherein the conversion unit comprises a hardware state machine.

26. The system of claim 21, wherein the conversion unit comprises a microcoded state machine.

27. The system of claim 21, wherein the conversion unit comprises a software agent running on an embedded processor.

28. A method, comprising:

receiving first storage protocol commands via a first I/O interface;

outputting second storage protocol commands via a second I/O interface;

converting at least some of the received first storage protocol commands into the second storage protocol commands via a conversion unit; and

wherein a first storage protocol de-allocation command of the first storage protocol commands is received in a first format by the first I/O interface and is converted and output in a second format as a second storage protocol de-allocation command of the second storage protocol commands.

29. The method of claim 28, wherein the storage protocol de-allocation commands are logical block de-allocation commands comprising at least one logical block address.

30. The method of claim 28, further comprising receiving and responding to the second storage protocol commands by mass storage.

31. The method of claim 30, further comprising generating the first storage protocol commands by an initiator.

32. The method of claim 31, further comprising receiving the first storage protocol commands by an expander and forwarding the first storage protocol commands to the first I/O interface by the expander.

33. The method of claim 28, wherein the first I/O interface, the second I/O interface, and the conversion unit are implemented as a unified assembly.

34. The method of claim 33, wherein the unified assembly is a bridge unit, the method further comprising generating the first storage protocol commands in an initiator unit, and receiving and responding to the second storage protocol commands by a mass storage unit.

35. The method of claim 28, wherein the first storage protocol commands are compatible with SCSI protocol commands and the second storage protocol commands are compatible with ATA protocol commands.

36. The method of claim 35, wherein the first storage protocol de-allocation command is a SCSI UNMAP command and the second storage protocol de-allocation command is an ATA data set management command.

37. The method of claim 35, wherein the first storage protocol de-allocation command is a command to write a pattern of data.

38. The method of claim 37, wherein the command to write a pattern of data is a selected one of a WRITE SAME command and a FORMAT command.

39. The method of claim 37, wherein the pattern of data is in accordance with a predetermined criteria.

40. The method of claim 28, wherein the first storage protocol commands are compatible with SAS protocol commands and the second storage protocol commands are compatible with SATA protocol commands.

41. The method of claim 30, wherein the mass storage is implemented using flash memory.

42. The method of claim 30, wherein the mass storage is a solid-state drive.

43. The method of claim 30, wherein the first I/O interface, the second I/O interface, the conversion unit, and the mass storage are implemented as a unified assembly.

44. The method of claim 43, wherein the unified assembly is a drive unit and further comprising generating the first storage protocol commands via an initiator unit.

45. The method of claim 44, wherein the mass storage is implemented using flash memory.

46. The method of claim 44, wherein the converting is implemented at least partially with dedicated logic.

47. The method of claim 44, wherein the converting is performed via at least one dedicated memory buffer.

48. The method of claim 44, wherein the converting comprises executing state transitions defined by a hardware state machine.

49. The method of claim 44, wherein the converting comprises executing state transitions defined by microcode.

50. The method of claim 44, wherein the converting comprises running a software agent on an embedded processor.

51. A apparatus, comprising:

first I/O interface means for receiving first storage protocol commands;

second I/O interface means for outputting second storage protocol commands; and

conversion means for converting at least some of the received first storage protocol commands into the second storage protocol commands, the converting comprising converting a first storage protocol de-allocation command of the first storage protocol commands and of a first format to a second storage protocol de-allocation command of the second storage protocol commands and of a second format.

52. The apparatus of claim 51, wherein the storage protocol de-allocation commands are logical block de-allocation commands comprising at least one logical block address.

53. The apparatus of claim 51, further comprising mass storage means for receiving and responding to the second storage protocol commands.

54. The apparatus of claim 53, further comprising an initiator means for generating the first storage protocol commands.

55. The apparatus of claim 54, further comprising expander means for receiving the first storage protocol commands and forwarding the first storage protocol commands to the first I/O interface means.

56. The apparatus of claim 51, wherein the first I/O interface means, the second I/O interface means, and the conversion means are implemented as a unified assembly.

57. The apparatus of claim 56, wherein the unified assembly is a bridge unit, the apparatus further comprising initiator means for generating the first storage protocol commands, and mass storage means for receiving and responding to the second storage protocol commands.

58. The apparatus of claim 51, wherein the first storage protocol commands are compatible with SCSI protocol commands and the second storage protocol commands are compatible with ATA protocol commands.

59. The apparatus of claim 58, wherein the first storage protocol de-allocation command is a SCSI UNMAP command and the second storage protocol de-allocation command is an ATA data set management command.

60. The apparatus of claim 58, wherein the first storage protocol de-allocation command is a command to write a pattern of data.

61. The apparatus of claim 60, wherein the command to write a pattern of data is a selected one of a WRITE SAME command and a FORMAT command.

62. The apparatus of claim 60, wherein the pattern of data is in accordance with a predetermined criteria.

63. The apparatus of claim 51, wherein the first storage protocol commands are compatible with SAS protocol commands and the second storage protocol commands are compatible with SATA protocol commands.

64. The apparatus of claim 53, wherein the mass storage means is implemented using flash memory.

65. The apparatus of claim 53, wherein the mass storage means is a solid-state drive.

66. The apparatus of claim 53, wherein the first I/O interface means, the second I/O interface means, the conversion means, and the mass storage means are implemented as a unified assembly.

67. The apparatus of claim 66, wherein the unified assembly is a drive unit and further comprising an initiator means for generating the first storage protocol commands.

68. The apparatus of claim 67, wherein the mass storage means is implemented using flash memory.

69. The apparatus of claim 67, wherein the conversion means comprises dedicated logic.

70. The apparatus of claim 67, wherein the conversion means comprises at least one dedicated memory buffer.

71. The apparatus of claim 67, wherein the conversion means comprises a hardware state machine.

72. The apparatus of claim 67, wherein the conversion means comprises a microcoded state machine.

73. The apparatus of claim 67, wherein the conversion means comprises a software agent running on an embedded processor.