NONVOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

• US 20120086057A1
• Filed: 10/04/2011
• Published: 04/12/2012
• Est. Priority Date: 10/06/2010
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: KIM, Jin Gu
• Granted Patent: US 8,502,295 B2
• Time in Patent Office: Days
• US Class Current: 257/288
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND

Abstract

A semiconductor memory device includes a gate insulating layer formed over a semiconductor substrate; a first conductive layer pattern for select transistors and memory cells formed on the gate insulating layer; a dielectric layer formed on the first conductive layer pattern; a second conductive layer pattern formed on the dielectric layer on the first conductive layer pattern for the memory cells; and select lines made of material having lower resistance than the second conductive layer pattern and coupled to the first conductive layer pattern for the select transistors.

Claims

1. A semiconductor memory device, comprising:

a gate insulating layer formed over first and second areas of a semiconductor substrate, wherein the first area is for forming a select transistor and the second area is for forming a memory cell;

a first conductive layer pattern for the select transistor and the memory cell formed over the gate insulating layer over the first and second areas;

a dielectric layer formed over the first conductive layer pattern over the first and second areas;

a second conductive layer pattern formed on the dielectric layer over the first conductive layer pattern for the memory cell; and

a select line having a lower resistance than the second conductive layer pattern and coupled to the first conductive layer pattern for the select transistor.

2. The semiconductor memory device of claim 1, wherein the second conductive layer pattern is further formed on the dielectric layer on the first conductive layer pattern for the select transistor in the first area.

3. The semiconductor memory device of claim 2, further comprising a first interlayer dielectric layer for insulating the select lines from the second conductive layer pattern formed on the first conductive layer pattern for the select transistor in the first area.

4. The semiconductor memory device of claim 1, further comprising a spacer formed on sidewalls of the first conductive layer pattern, the dielectric layer, and the second conductive layer pattern in each of the first and second areas.

5. The semiconductor memory device of claim 1, further comprising an auxiliary line having a lower resistance than the second conductive layer pattern and coupled to the select line.

6. The semiconductor memory device of claim 5, wherein the auxiliary line is formed of metal.

7. The semiconductor memory device of claim 5, wherein the auxiliary line comprises tungsten (W), cobalt (Co), or nickel (Ni) or a metal silicide layer.

8. The semiconductor memory device of claim 1, wherein the second conductive layer pattern has a stack structure of a polysilicon layer and a metal silicide layer.

9. The semiconductor memory device of claim 1, wherein the select line comprises metal.

10. The semiconductor memory device of claim 1, further comprising:

junctions of the select transistor formed in the first area of the semiconductor substrate; and

a common source line coupled to the junctions,

wherein the select line is made of a substantially same material as the material of the common source line.

11. A method of manufacturing a semiconductor memory device, the method comprising:

stacking a first conductive layer, a dielectric layer, and a second conductive layer over a semiconductor substrate;

forming a first conductive layer pattern for select transistors and memory cells and a second conductive layer pattern by etching the second conductive layer, the dielectric layer, and the first conductive layer;

etching the second conductive layer pattern over the first conductive layer pattern for the select transistors so at to expose the dielectric layer;

forming a first interlayer dielectric layer over the semiconductor substrate to fill the etched parts of the second conductive layer pattern;

etching the first interlayer dielectric layer and the dielectric layer to expose the first conductive layer pattern for the select transistors; and

forming select lines coupled to the first conductive layer pattern by filling the etched parts of the first interlayer dielectric layer and the dielectric layer with a material having a lower resistance than the material of the second conductive layer pattern.

12. The method of claim 11, wherein when exposing the dielectric layer by etching the second conductive layer pattern, a width of the exposed dielectric layer is substantially identical to a width of the first conductive layer pattern for the select transistors or substantially narrower than a width of the first conductive layer pattern for the select transistors.

13. The method of claim 11, further comprising forming a spacer on sidewalls of the second conductive layer pattern, the dielectric layer, and the first conductive layer pattern, before etching the second conductive layer pattern.

14. The method of claim 13, wherein the spacer and the dielectric layer are used as etch-stop layers when etching the second conductive layer pattern.

15. The method of claim 11, wherein forming a first interlayer dielectric layer over the semiconductor substrate comprises:

forming a first insulating layer to fill the etched parts of the second conductive layer pattern;

polishing the first insulating layer to expose the second conductive layer pattern; and

forming a second insulating layer on the first insulating layer including the second conductive layer pattern.

16. The method of claim 15, further comprising performing a *silidation process to change an upper portion of the second conductive layer pattern into a metal silicide layer, before forming the second insulating layer.

17. The method of claim 11, wherein the second conductive layer comprises polysilicon.

18. The method of claim 11, further comprising:

forming a second interlayer dielectric layer over the first interlayer dielectric layer including the select lines;

etching the second interlayer dielectric layer to expose the select lines; and

forming auxiliary lines coupled to the select lines by filling the etched parts of the second interlayer dielectric layer with material having lower resistance than material of the second conductive layer pattern.

19. The method of claim 18, wherein the auxiliary lines comprise metal.

20. The method of claim 18, wherein the auxiliary lines comprise tungsten (W), cobalt (Co), or nickel (Ni) or formed of metal silicide layers.

21. The method of claim 11, wherein the select lines comprise metal.

22. The method of claim 11, wherein the select lines comprise tungsten (W), cobalt (Co), or nickel (Ni) or formed of metal silicide layers.

23. The method of claim 11, further comprising forming junctions of the select transistors by implanting impurity ions into the semiconductor substrate, after forming the first and second conductive layer patterns.

24. The method of claim 23, wherein:

the junctions are exposed when etching the first interlayer dielectric layer and the dielectric layer, and

a common source line coupled to the junctions is formed simultaneously with the select lines when forming the select lines.