METHOD FOR DEPOSITING A DIELECTRIC ONTO A FLOATING GATE FOR STRAINED SEMICONDUCTOR DEVICES

• US 20120086068A1
• Filed: 10/06/2010
• Published: 04/12/2012
• Est. Priority Date: 10/06/2010
• Status: Abandoned Application

• Current Assignee: Synopsys Incorporated
• Original Assignee: Synopsys Incorporated
• Inventors: Horch, Andrew E.
• Application Number:
  US12/898,737
• Publication Number:
  US 20120086068A1
• Time in Patent Office: Days
• US Class Current: 257/324
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence

Abstract

A method for forming a semiconductor device and a corresponding device are provided. The method includes forming a floating gate device in a process with dual strain layers, and an etch stop layer. An oxide is formed between the floating gate device and a nitride layer above the floating gate.

Claims

24. A semiconductor device having a semiconductor body, the semiconductor device comprising:

a floating gate device;

a second device of first dopant type, the first dopant type being n-type such that the second device comprises an n-type metal oxide semiconductor (NMOS) device;

a third device of a second dopant type, wherein the second dopant type is p-type such that the third device comprises a p-type metal oxide semiconductor (PMOS) device, the third device being coupled between the floating gate device and the second device;

a first stress layer deposited above at least the second device;

a second stress layer deposited above at least the third device;

a dielectric layer deposited above the floating gate device after depositing the first and second stress layers; and

an etch stop layer fabricated above the first stress layer, second stress layer, and the dielectric layer.

25. The semiconductor device of claim 24, wherein one of the stress layers comprises a tensile layer disposed above the NMOS device, and other stress layer comprises a compressive layer disposed above the PMOS device.

26. The semiconductor device of claim 24, wherein the first stress layer and second stress layer each comprise a nitride layer.

27. The semiconductor device of claim 24, wherein the first stress layer forms a tensile layer and the second stress layer forms a compressive layer.

28. The semiconductor device of claim 24, wherein the second stress layer comprises a compressive layer.

29. The semiconductor device of claim 24, wherein the dielectric layer comprises a silicon dioxide (SiO₂) layer.

30. The semiconductor device of claim 24, further comprising a double spacer formed on sidewalls of a gate stack of the floating gate device, the double spacer including a first dielectric spacer and a second dielectric spacer.

31. The semiconductor device of claim 30, wherein the first dielectric spacer comprises a silicon oxide spacer.

32. The semiconductor device of claim 30, wherein the second dielectric spacer comprises a silicon nitride spacer.

33. The semiconductor device of claim 30, wherein the second dielectric spacer is removed from atop the gate stack of the floating gate device before depositing the dielectric layer.

34. The semiconductor device of claim 30, wherein the first and second stress layers are deposited above the gate stack of the floating gate device, and the first and second stress layers are removed from the gate stack of the floating gate device using a respective etch after deposition of each of the respective stress layers.

35. The semiconductor device of claim 34, further comprising, during the respective etches, removing the second dielectric spacer from atop the gate stack of the floating gate.

37. The semiconductor device of claim 24, wherein the semiconductor device comprises a non-volatile memory (NVM) device.

38. The semiconductor device of claim 24, further comprising interconnections between the floating gate device, the second device, and the third device.

36-1. The semiconductor device of claim 36, further comprising a conductive film deposited atop the dielectric layer above the floating gate device, wherein the conductive film comprises a doped poly silicon or a metal.

39. A semiconductor device formed on a substrate, the semiconductor device comprising:

a PMOS device having a compressive film thereover;

an NMOS device having a tensile film thereover;

a salicide block layer at least partially comprised of nitride; and

a floating gate device having an SiO₂ dielectric layer deposited thereon, the salicide block layer being deposited at least on the floating gate device, such that the SiO₂ dielectric layer is positioned atop the floating gate device and beneath any of the nitride deposited on the floating gate device; and

an etch stop layer deposited over the PMOS, NMOS, and floating gate devices.

40. A semiconductor device formed on a substrate, the semiconductor device comprising:

a PMOS device having a compressive film thereover;

an NMOS device having a tensile film thereover;

a floating gate device having an oxide film and a conductive film deposited thereon, the conductive film being formed over the oxide film and beneath any nitride deposited on the floating gate device; and

an etch stop layer over the NMOS, PMOS, and floating gate devices formed in the substrate.