STRESS MEMORIZATION PROCESS IMPROVEMENT FOR IMPROVED TECHNOLOGY PERFORMANCE

• US 20120086071A1
• Filed: 10/12/2010
• Published: 04/12/2012
• Est. Priority Date: 10/12/2010
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Doris, Bruce B., Mehta, Sanjay, Zhu, Zhengmao, Adam, Lahir Shaik
• Granted Patent: US 8,535,999 B2
• Time in Patent Office: Days
• US Class Current: 257/327
• CPC Class Codes: H01L 29/7847 using a memorization technique, e.g. re-crystallization under strain, bonding on a substrate having a thermal expansion coefficient different from the one of the region

Abstract

Semiconductor substrate with a deformed gate region and a method for the fabrication thereof. The semiconductor substrate has improved device performance compared to devices without a deformed gate region and decreased dopant loss compared to devices with deformed source/drain regions.

Claims

1. A method of fabricating a semiconductor structure, comprising:

providing a semiconductor substrate;

forming a gate structure on the semiconductor substrate;

forming a source-drain implant region adjacent to the gate structure;

forming a stress-transmitting dielectric layer on the source-drain implant region and the gate structure;

removing the stress-transmitting dielectric layer; and

performing an annealing step after the removing of the stress-transmitting dielectric layer.

2. The method of claim 1, wherein the stress-transmitting dielectric layer is a compressive stress-transmitting dielectric layer.

3. The method of claim 1, wherein the stress-transmitting dielectric layer is a tensile stress-transmitting dielectric layer.

4. The method of claim 1, further comprising transferring a uniaxial compressive stress from the stress-transmitting dielectric layer to the gate structure.

5. The method of claim 4, wherein the uniaxial compressive stress in the gate structure is of from about 300 MPa to about 3 GPa.

6. The method of claim 1, wherein annealing step is effected at a temperature of from about 950°

C. to about 1,200°

C.

7. The method of claim 1, wherein the stress-transmitting dielectric layer is a refractory metal nitride.

8. The method of claim 7, wherein the refractory metal nitride is selected from the group consisting of TaN, TiN, WN, MoN, NbN, ReN, and a combination thereof.

9. The method of claim 8, wherein the refractory metal nitride is TiN.

10. The method of claim 1, wherein a carrier concentration is substantially unchanged before and after the annealing step.

11. The method of claim 10, wherein the carrier is selected from the group consisting of a hole h⁺ and an electron e⁻

.

12. The method of claim 1, further comprising applying a capping layer on the source-drain implant region prior to the forming of the stress-transmitting dielectric layer.

13. The method of claim 1, wherein the stress-transmitting dielectric layer is a silicon oxide.

14. The method of claim 1, wherein the stress-transmitting dielectric layer exerts a pressure of from about 300 MPa to about 3 GPa.

15. A semiconductor structure comprising:

a semiconductor substrate;

a gate structure on the semiconductor substrate; and

a source-drain implant region adjacent to the gate structure;

wherein the gate structure is deformed.

16. The semiconductor structure of claim 15, wherein the deformed gate structure is compressed in a direction perpendicular to the semiconductor substrate.

17. The semiconductor structure of claim 15, wherein the deformed gate structure is elongated in a direction perpendicular to the semiconductor substrate.

18. The semiconductor structure of claim 15, further comprising a shallow trench isolation between the source-drain implant region and the gate structure.

19. The semiconductor structure of claim 15, wherein the gate structure is deformed by a compressive stress or a tensile stress of from about 5 GPa to about 20 GPa.

20. The semiconductor structure of claim 15, wherein the gate structure is deformed by a compressive stress or a tensile stress of from about 300 MPa to about 3 GPa.

21. A n-type metal-oxide semiconductor or a p-type metal-oxide semiconductor comprising the semiconductor structure of claim 15.