PACKAGE SYSTEMS AND MANUFACTURING METHODS THEREOF

• US 20120086126A1
• Filed: 10/08/2010
• Published: 04/12/2012
• Est. Priority Date: 10/08/2010
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: SHU, Chia-Pao, CHENG, Chun-wen, CHANG, Kuei-Sung
• Granted Patent: US 9,000,578 B2
• Time in Patent Office: Days
• US Class Current: 257/773
• CPC Class Codes: B81C 1/00238 Joining a substrate with an electronic processing unit and a substrate with a micromechanical structure
• CPC Class Codes: B81C 1/00269 Bonding of solid lids or wafers to the substrate
• CPC Class Codes: B81C 2203/019 characterised by the material or arrangement of seals between parts
• CPC Class Codes: H01L 2224/0345 Physical vapour deposition [PVD], e.g. evaporation, or sputtering
• CPC Class Codes: H01L 2224/03452 Chemical vapour deposition [CVD], e.g. laser CVD
• CPC Class Codes: H01L 2224/0361 Physical or chemical etching
• CPC Class Codes: H01L 2224/0362 Photolithography
• CPC Class Codes: H01L 2224/04026 Bonding areas specifically adapted for layer connectors
• CPC Class Codes: H01L 2224/05551 comprising apertures or cavities
• CPC Class Codes: H01L 2224/05555 being circular or elliptic
• CPC Class Codes: H01L 2224/05557 comprising protrusions or indentations
• CPC Class Codes: H01L 2224/05617 the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
• CPC Class Codes: H01L 2224/05638 the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
• CPC Class Codes: H01L 2224/061 Disposition
• CPC Class Codes: H01L 2224/26145 Flow barriers
• CPC Class Codes: H01L 2224/29017 being non uniform along the layer connector
• CPC Class Codes: H01L 2224/2902 Disposition
• CPC Class Codes: H01L 2224/29101 the principal constituent melting at a temperature of less than 400°C
• CPC Class Codes: H01L 2224/29111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/29117 the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
• CPC Class Codes: H01L 2224/29124 : Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/29138 : the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
• CPC Class Codes: H01L 2224/29144 : Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/29147 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/29155 : Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/29166 : Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/29181 : Tantalum [Ta] as principal constituent
• CPC Class Codes: H01L 2224/29291 : The principal constituent being an elastomer, e.g. silicones, isoprene, neoprene
• CPC Class Codes: H01L 2224/32058 : being non uniform along the layer connector
• CPC Class Codes: H01L 2224/321 : Disposition
• CPC Class Codes: H01L 2224/32106 : the layer connector connecting one bonding area to at least two respective bonding areas
• CPC Class Codes: H01L 2224/32148 : the layer connector connecting to a bonding area protruding from the surface
• CPC Class Codes: H01L 2224/83203 : Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
• CPC Class Codes: H01L 2224/83365 : Shape, e.g. interlocking features
• CPC Class Codes: H01L 2224/83805 : involving forming a eutectic alloy at the bonding interface
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/30 : of a plurality of layer connectors
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01032 : Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01037 : Rubidium [Rb]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/0132 : Binary Alloys
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1461 : MEMS

Abstract

A package system includes a first substrate and a second substrate. The second substrate is electrically coupled with the first substrate. The second substrate includes at least one first opening. At least one electrical bonding material is disposed between the first substrate and the second substrate. A first portion of the at least one electrical bonding material is at least partially filled in the at least one first opening.

Claims

1. A package system comprising:

a first substrate;

a second substrate electrically coupled with the first substrate, the second substrate comprising at least one first opening; and

at least one electrical bonding material disposed between the first substrate and the second substrate, wherein a first portion of the at least one electrical bonding material is at least partially filled in the at least one first opening.

2. The package system of claim 1, wherein the at least one electrical bonding material is a eutectic bonding material, the eutectic bonding material includes a metallic material and a semiconductor material, and the semiconductor material is disposed over the first substrate.

3. The package system of claim 2, wherein the semiconductor material includes a pad and at least one guard ring around the pad.

4. The package system of claim 3, wherein a gap is formed between the pad and the at least one guard ring, and the at least one first opening faces at least one of the pad and the gap.

5. The package system of claim 1, wherein the first substrate comprises at least one second opening, and the at least one second opening is configured to accommodate at least a second portion of the at least one electrical bonding material.

6. The package system of claim 5, wherein the at least one first and second openings do not penetrate all the way through the second and first substrates, respectively.

7. The package system of claim 5, wherein the at least one second opening is misaligned from the at least one first opening.

8. A package system comprising:

a first substrate comprising a semiconductor pad;

a second substrate comprising a metallic pad electrically coupled with the semiconductor pad, wherein at least one of the first and second substrates comprises at least one opening in which a portion of a material of the metallic pad is at least partially filled.

9. The package system of claim 8, wherein the metallic pad and the semiconductor pad are configured to form a eutectic bonding between the first and second substrates.

10. The package system of claim 8, wherein the at least one opening comprises at least one first trench opening and the at least one first trench opening is disposed in the second substrate.

11. The package system of claim 10, wherein the at least one opening further comprises at least one second trench opening, and the at least one second trench opening is disposed in the first substrate and around the semiconductor pad.

12. The package system of claim 11, wherein the second substrate further comprises at least one guard ring disposed around the semiconductor pad.

13. The package system of claim 12, wherein a gap is formed between the semiconductor pad and the at least one guard ring, and the at least one first trench opening faces at least one of the semiconductor pad and the gap.

14. The package system of claim 11, wherein the at least one first and second trench openings do not penetrate all the way through the first and second substrates.

15. The package system of claim 11, wherein the at least one second trench opening is misaligned from the at least one first trench opening.

16. A method of forming a package system, the method comprising:

providing a first substrate;

bonding the first substrate and a second substrate through at least one electrical bonding material between the first and second substrate, the second substrate comprising at least one first opening, wherein the bonding process pushes a first portion of the at least one electrical bonding material at least partially filling in the at least one first opening.

17. The method of claim 16, wherein bonding the first and second substrates comprises:

eutectic bonding a semiconductor pad on the first substrate and a metallic pad on the second substrate.

18. The method of claim 17, further comprising:

forming at least one guard ring around the semiconductor pad.

19. The method of claim 16, further comprising:

forming at least one second opening in the first substrate, wherein bonding the first and second substrates pushes at least a second portion of the at least one electrical bonding material at least partially filling in the at least one second opening.

20. The method of claim 19, wherein the at least one first and second openings do not penetrate all the way through the second and first substrates, respectively.