INTEGRATED JITTER COMPLIANT CLOCK SIGNAL GENERATION

• US 20120086491A1
• Filed: 10/07/2010
• Published: 04/12/2012
• Est. Priority Date: 10/07/2010
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Cortina Systems Incorporated (Inphi Corporation)
• Inventors: Scouten, Shawn, Stevens, Malcolm, Parker, Kevin
• Granted Patent: US 8,390,358 B2
• Time in Patent Office: Days
• US Class Current: 327/295
• CPC Class Codes: H03L 7/23 with pulse counters or frequency dividers

Abstract

Integrated jitter compliant clock signal generation apparatus and methods are provided. Input signals having different frequencies are used to generate respective clock signals having closely spaced frequencies. The input signals might be generated, for example, in adjacent Phase Locked Loops (PLLs) which receive reference clock signals. The reference clock signals, or signals from which the reference clock signals originate, are also closely spaced. The closely spaced reference clock signals are effectively separated for cleanup and then brought back together to provide the closely spaced clock signals. This allows cleanup of the closely spaced reference clock signals to occur at staggered and more widely spaced frequencies. These techniques could also be applied to reference clock signals which are harmonically related and are used to generate harmonically related output clock signals.

Claims

1. An apparatus comprising:

a plurality of adjacent Phase Locked Loops (PLLs) to provide respective PLL output signals having respective different frequencies; and

a clock unit operatively coupled to receive the respective PLL output signals and to generate from the PLL output signals respective clock signals, the respective clock signals having closely spaced frequencies.

2. The apparatus of claim 1, further comprising:

a reference clock signal source, operatively coupled to provide respective reference clock signals having respective different frequencies to the plurality of PLLs.

3. The apparatus of claim 1, further comprising:

a reference clock signal source, operatively coupled to provide to the plurality of PLLs respective reference clock signals having closely spaced frequencies,

the plurality of PLLs applying respective different frequency multiplication factors to the respective reference clock signals to provide the respective PLL output signals.

4. The apparatus of claim 1, wherein the clock unit comprises:

a plurality of adjacent clock unit modules respectively operatively coupled to receive the PLL output signals and to generate the respective clock signals.

5. The apparatus of claim 4, wherein each clock unit module comprises:

an integer frequency divider operatively coupled to receive a respective one of the PLL output signals and to provide a divided output signal having a frequency that is a fraction of the frequency of the respective one of the PLL output signals; and

an integer frequency multiplier operatively coupled to receive the divided output signal and to provide one of the respective clock signals having a frequency that is a multiple of the frequency of the divided output signal.

6. The apparatus of claim 4, wherein each clock unit module comprises:

a fractional frequency multiplier operatively coupled to receive a respective one of the PLL output signals and to generate one of the respective clock signals having a frequency that is a fractional multiple of the frequency of the respective one of the PLL output signals.

7. The apparatus of claim 4, wherein each clock unit module comprises a Clock Multiplier Unit (CMU), each CMU comprising a further PLL.

8. The apparatus of claim 7, wherein the PLL of each CMU of each clock unit module has a wider bandwidth than the plurality of PLLs.

9. An apparatus comprising:

an input to receive a plurality of input signals having respective different frequencies; and

a clock unit operatively coupled to receive the plurality of input signals and to generate from the input signals respective clock signals, the respective clock signals having closely spaced frequencies.

10. The apparatus of claim 9, wherein the clock unit comprises:

a plurality of adjacent clock unit modules respectively operatively coupled to receive the PLL output signals and to generate the respective clock signals.

11. The apparatus of claim 10, wherein each clock unit module comprises:

an integer frequency divider operatively coupled to receive a respective one of the input signals and to provide a divided output signal having a frequency that is a fraction of the frequency of the respective one of the input signals; and

an integer frequency multiplier operatively coupled to receive the divided output signal and to provide one of the respective clock signals having a frequency that is a multiple of the frequency of the divided output signal.

12. The apparatus of claim 10, wherein each clock unit module comprises:

a fractional frequency multiplier operatively coupled to receive a respective one of the input signals and to generate one of the respective clock signals having a frequency that is a fractional multiple of the frequency of the respective one of the input signals.

13. The apparatus of claim 10, wherein

the input signals comprise signals generated by a plurality of Phase Locked Loops (PLLs),

each clock unit module comprises a Clock Multiplier Unit (CMU), each CMU comprising a further PLL,

the PLL of each CMU of each clock unit module has a wider bandwidth than the plurality of PLLs.

14. A method comprising:

receiving a plurality of input signals having respective different frequencies; and

generating from the input signals respective clock signals, the respective clock signals having closely spaced frequencies.

15. The method of claim 14, further comprising:

generating the plurality of input signals in respective adjacent Phase Locked Loops (PLLs).

16. The method of claim 15, further comprising:

providing respective reference clock signals having respective different frequencies to the respective PLLs.

17. The method of claim 15, further comprising:

providing to the respective PLLs respective reference clock signals having closely spaced frequencies,

each PLL applying a respective different frequency multiplication factor to its respective reference clock signals to provide a respective one of the input signals.

18. The method of claim 14, wherein generating comprises, for each respective clock signal:

an integer frequency divide operation to provide a respective divided output signal having a frequency that is a fraction of the frequency of a respective one of the input signals; and

an integer frequency multiply operation to receive the divided output signal and to provide one of the respective clock signals having a frequency that is a multiple of the frequency of the divided output signal.

19. The method of claim 14, wherein generating comprises, for each respective clock signal:

a fractional frequency multiply operation to generate one of the respective clock signals having a frequency that is a fractional multiple of the frequency of a respective one of the input signals.

20. The method of claim 15, wherein generating respective clock signals comprises generating the respective clock signals in respective further PLLs, each of the further PLLs having a wider bandwidth than the respective adjacent PLLs.

21. An apparatus comprising:

a plurality of adjacent Phase Locked Loops (PLLs) to provide respective PLL output signals having respective different frequencies; and

a clock unit operatively coupled to receive the respective PLL output signals and to generate from the PLL output signals respective clock signals, the respective clock signals having harmonically related frequencies.