Techniques for Adjusting Clock Signals to Compensate for Noise

• US 20120087452A1
• Filed: 05/31/2010
• Published: 04/12/2012
• Est. Priority Date: 06/30/2009
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Zerbe, Jared, Batra, Pradeep, Leibowitz, Brian
• Granted Patent: US 9,565,036 B2
• Time in Patent Office: Days
• US Class Current: 375/354
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew
• CPC Class Codes: H03K 5/1252 Suppression or limitation of noise or interference specially adapted for transmission systems H04B15/00, H04L25/08
• CPC Class Codes: H04L 25/0264 Arrangements for coupling to transmission lines duplexing arrangements H04L5/14; line equalisers, line build-out devices H04L25/03878

Abstract

A first integrated circuit (IC) has an adjustable delay circuit and a first interface circuit. A first clock signal is provided to the adjustable delay circuit to produce a delayed clock signal provided to the first interface circuit. A second IC has a supply voltage sense circuit and a second interface circuit that transfers data with the first IC. The supply voltage sense circuit provides a noise signal to the first IC that is indicative of noise in a supply voltage of the second IC. The adjustable delay circuit adjusts a delay of the delayed clock signal based on the noise signal. In other embodiments, edge-colored clock signals reduce the effects of high frequency jitter in the transmission of data between integrated circuits (ICs) by making the high frequency jitter common between the ICs. In other embodiments, a supply voltage is used to generate clocks signals on multiple ICs.

Claims

1-58. -58. (canceled)

59. A system comprising:

a first integrated circuit device comprising;

a first internal clock buffer circuit, which draws current that is sourced from a first supply voltage, the first internal clock buffer circuit to provide a first internal clock signal; and

a first interface circuit to output data synchronously with respect to the first internal clock signal; and

a second integrated circuit device comprising;

a second internal clock buffer circuit, which draws current that is sourced from the first supply voltage, the second internal clock buffer circuit to generate a second internal clock signal; and

a second interface circuit to receive the data synchronously with respect to the second internal clock signal.

60. The system of claim 59, wherein the first supply voltage is common to the first and the second integrated circuit devices via a conductor.

61. The system of claim 59, wherein at least one of the first and the second integrated circuit devices further comprises a regulator circuit that generates a second supply voltage using the first supply voltage such that one of the respective first and second internal clock buffer circuits draws current that is sourced from the first supply voltage via the second supply voltage.

62. The system of claim 59 wherein at least one of the first and the second integrated circuit devices draws current from a second supply voltage that is derived from the first supply voltage.

63. The system of claim 59 wherein the first supply voltage is provided to the first integrated circuit device and to the second integrated circuit device from a source that is external to the first and the second integrated circuit devices.

64. The system of claim 59 wherein the first integrated circuit device further includes a clock receiver circuit, wherein the first internal clock signal is derived from an external timing signal that is received at the clock receiver circuit, and wherein the external timing signal is provided by the second integrated circuit device.

65. The system of claim 59 wherein the second integrated circuit device further includes a clock receiver circuit, wherein the second internal clock signal is derived from an external timing signal that is received at the clock receiver circuit, and wherein the external timing signal is provided by the first integrated circuit device.

66. The system of claim 59 wherein one of the first and the second integrated circuit devices is a memory device and the other of the first and the second integrated circuit devices is a controller device.

67. A first integrated circuit comprising:

a first clock buffer circuit, which draws current that is sourced from a first supply voltage, the first clock buffer circuit to provide a first internal clock signal; and

an interface circuit to output data to a second integrated circuit, synchronously with respect to the first internal clock signal, wherein the second integrated circuit receives the data synchronously with respect to a second internal clock signal, wherein the second internal clock signal is generated by a second clock buffer circuit, which draws current that is sourced from the first supply voltage.

68. The first integrated circuit of claim 67, wherein a delay characteristic of the first clock buffer circuit varies with respect to noise present in the first supply voltage.

69. The first integrated circuit of claim 67, wherein the first supply voltage is generated in the second integrated circuit.

70. The first integrated circuit of claim 67, wherein the first clock buffer circuit is part of an on chip clock distribution network.

71. The first integrated circuit of claim 67, wherein at least one of the first and the second integrated circuits further comprises a regulator circuit that generates a second supply voltage using the first supply voltage such that one of the respective first and second clock buffer circuits draws current that is sourced from the first supply voltage via the second supply voltage.

72. The first integrated circuit of claim 67, wherein the interface circuit draws current from a second supply voltage that is derived from the first supply voltage.

73. The first integrated circuit of claim 67, wherein the first supply voltage is provided to the first integrated circuit and to the second integrated circuit from a source that is external to the first and the second integrated circuits.

74. The first integrated circuit of claim 67, wherein the first integrated circuit further includes a clock receiver circuit, wherein the first internal clock signal is derived from an external timing signal that is received at the clock receiver circuit, and wherein the external timing signal is provided by the second integrated circuit.

75. The first integrated circuit of claim 67, wherein the second integrated circuit further includes a clock receiver circuit, wherein the second internal clock signal is derived from an external timing signal that is received at the clock receiver circuit, and wherein the external timing signal is provided by the first integrated circuit.

76. The first integrated circuit of claim 67, wherein one of the first and the second integrated circuits is a memory device and the other of the first and the second integrated circuits is a controller device.

77. A first integrated circuit comprising:

a first clock buffer circuit, which draws current that is sourced from a first supply voltage, the first clock buffer circuit to provide a first internal clock signal; and

an interface circuit to receive data from a second integrated circuit, synchronously with respect to the first internal clock signal, wherein the second integrated circuit transmits the data to the first integrated circuit synchronously with respect to a second internal clock signal, wherein the second internal clock signal is generated by a second clock buffer circuit, which draws current that is sourced from the first supply voltage.

78. The first integrated circuit of claim 77, wherein the first supply voltage is common to the first and the second integrated circuits via a conductor.

79. The first integrated circuit of claim 77, wherein at least one of the first and the second integrated circuits further comprises a regulator circuit that generates a second supply voltage using the first supply voltage such that one of the respective first and second clock buffer circuits draws current that is sourced from the first supply voltage via the second supply voltage.

80. The first integrated circuit of claim 77, wherein the interface circuit draws current from a second supply voltage that is derived from the first supply voltage.

81. The first integrated circuit of claim 77, wherein the first supply voltage is provided to the first integrated circuit and to the second integrated circuit from a source that is external to the first and the second integrated circuits.

82. The first integrated circuit of claim 77, wherein the first integrated circuit further includes a clock receiver circuit, wherein the first internal clock signal is derived from an external timing signal that is received at the clock receiver circuit, and wherein the external timing signal is provided by the second integrated circuit.

83. The first integrated circuit of claim 77, wherein the second integrated circuit further includes a clock receiver circuit, wherein the second internal clock signal is derived from an external timing signal that is received at the clock receiver circuit, and wherein the external timing signal is provided by the first integrated circuit.

84. The first integrated circuit of claim 77, wherein a delay characteristic of the first clock buffer circuit varies with respect to noise present in the first supply voltage.

85. The first integrated circuit of claim 77, wherein the first supply voltage is generated in the second integrated circuit.

86. A method of operation of a first integrated circuit device, the method comprising:

drawing current in a first clock buffer circuit to provide a first internal clock signal, wherein the current is sourced from a first supply voltage; and

transferring data with a second integrated circuit device, synchronously with respect to the first internal clock signal, wherein the second integrated circuit device transmits the data with the first integrated circuit device synchronously with respect to a second clock signal, wherein the second clock signal is generated by a second clock buffer circuit, which draws current that is sourced from the first supply voltage.

87. The method of claim 86 wherein the first supply voltage is common to the first and the second integrated circuit devices via a conductor.

88. The method of claim 86 further comprising:

generating a second supply voltage using the first supply voltage such that one of the respective first and second clock buffer circuits draws current that is sourced from the first supply voltage via the second supply voltage.

89. The method of claim 86 further comprising:

drawing current in at least one of the first and the second integrated circuit devices from a second supply voltage that is derived from the first supply voltage.

90. The method of claim 86 further comprising:

receiving the first supply voltage at the first integrated circuit device and at the second integrated circuit device from a source that is external to the first and the second integrated circuit devices.

91. The method of claim 86 further comprising:

generating the first internal clock signal from an external timing signal using a clock receiver circuit in the first integrated circuit device, wherein the external timing signal is provided by the second integrated circuit device.

92. The method of claim 86 further comprising:

generating the second clock signal from an external timing signal using a clock receiver circuit in the second integrated circuit device, wherein the external timing signal is provided by the first integrated circuit device.

93. The method of claim 86 wherein the first supply voltage is generated in the second integrated circuit device.

94. The method of claim 86 wherein a delay characteristic of the first clock buffer circuit varies with respect to noise present in the first supply voltage.