SHARED RESOURCE MULTI-THREAD PROCESSOR ARRAY
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Abstract
A shared resource multi-thread processor array wherein an array of heterogeneous function blocks are interconnected via a self-routing switch fabric, in which the individual function blocks have an associated switch port address. Each switch output port comprises a FIFO style memory that implements a plurality of separate queues. Thread queue empty flags are grouped using programmable circuit means to form self-synchronised threads. Data from different threads are passed to the various addressable function blocks in a predefined sequence in order to implement the desired function. The separate port queues allows data from different threads to share the same hardware resources and the reconfiguration of switch fabric addresses further enables the formation of different data-paths allowing the array to be configured for use in various applications.
150 Citations
50 Claims
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1-30. -30. (canceled)
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31. An array processor capable of multi-threaded processing comprising:
- one or a plurality of thread coordinators;
one or a plurality of self-routing switch fabrics;
an array of addressable heterogeneous function blocks, each heterogeneous function block input port being connected directly to a buffered output port of a self-routing switch fabric, each group of buffered output ports within each heterogeneous function block comprising at least a thread queue scheduler;
wherein each buffered output port implements one or a plurality of independent thread queues, each thread queue having at least an empty flag output, where the empty flag outputs are configured into groups of any combination via programmable circuit means to form one or more groups of coupled thread queues;
each thread queue scheduler is configured to simultaneously read tokens from selected thread queues and transfer them to the connected heterogeneous function block; and
each heterogeneous function block is configured to perform operations upon input data, format resultant data as a token by at least appending a routing tag to the resultant data and transfer said token via the self-routing switch fabric to a thread coordinator or the next heterogeneous function block. - View Dependent Claims (32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47)
- one or a plurality of thread coordinators;
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48. An array processor capable of multi-threaded processing comprising:
- one or a plurality of thread coordinators;
one or a plurality of self-routing switch fabrics;
an array of addressable heterogeneous function blocks, each heterogeneous function block input port being connected directly to a buffered output port of a self-routing switch fabric, each buffered output port comprising at least a scheduler;
wherein each buffered output port implements one or a plurality of independent thread queues, each thread queue having at least an empty flag output, where the empty flag outputs are grouped using logic gates to form one or more groups of coupled thread queues;
each scheduler is configured to simultaneously read tokens from selected thread queues and transfer them to the connected heterogeneous function block;
each heterogeneous function block is configured to perform operations upon input data, format resultant data as a token by at least appending a routing tag to the resultant data and transfer said token via the self-routing switch fabric to a thread coordinator or the next heterogeneous function block. - View Dependent Claims (49, 50)
- one or a plurality of thread coordinators;
Specification