SYSTEMS AND METHODS FOR OPTIMIZING DATA STORAGE AMONG A PLURALITY OF SOLID STATE MEMORY SUBSYSTEMS

• US 20120089854A1
• Filed: 10/10/2011
• Published: 04/12/2012
• Est. Priority Date: 10/10/2010
• Status: Active Grant

• Current Assignee: Liqid Inc
• Original Assignee: Puresilicon, Inc.
• Inventors: Gupta, Alok, Breakstone, Jason, Desai, Himanshu, Campos, Angelo
• Granted Patent: US 8,688,926 B2
• Time in Patent Office: Days
• US Class Current: 713/323
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: G06F 1/30 Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations for resetting only G06F1/24
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: G06F 2213/0026 PCI express
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0613 in relation to throughput
• CPC Class Codes: G06F 3/0625 Power saving in storage systems
• CPC Class Codes: G06F 3/0653 Monitoring storage devices or systems
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0665 at area level, e.g. provisioning of virtual or logical volumes
• CPC Class Codes: G06F 3/0685 Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A solid state storage device includes an interface system configured to communicate with an external host system over an aggregated multi-channel interface to receive data for storage by the solid state storage device. The solid state storage device also includes a storage processing system configured to communicate with the interface system to receive the data, process the data against storage allocation information to parallelize the data among a plurality of solid state memory subsystems, and transfer the parallelized data. The interface system is configured to receive the parallelized data, apportion the parallelized data among the plurality of solid state memory subsystems, and transfer the parallelized data for storage in the plurality of solid state memory subsystems, where each of the plurality of solid state memory subsystems is configured to receive the associated portion of the parallelized data and store the associated portion on a solid state storage medium.

Claims

1. A solid state storage device, comprising:

an interface system configured to communicate with an external host system over an aggregated multi-channel interface to receive a write instruction and data for storage by the solid state storage device;

a storage processing system configured to communicate with the interface system to receive the data, process the data against storage allocation information to parallelize the data among a plurality of solid state memory subsystems, and transfer the parallelized data;

the interface system configured to receive the parallelized data, apportion the parallelized data among the plurality of solid state memory subsystems, and transfer the parallelized data for storage in the plurality of solid state memory subsystems;

wherein each of the plurality of solid state memory subsystems is configured to receive the associated portion of the parallelized data and store the associated portion on a solid state storage medium.

2. The solid state storage device of claim 1, comprising:

the interface system configured to communicate with the external host system over the aggregated multi-channel interface to receive a read instruction to retrieve existing data previously stored by the solid state storage device;

the storage processing system configured to communicate with the interface system to receive the read instruction, process the read instruction against the storage allocation information to determine parallelized read commands for ones of the plurality of solid state memory subsystems, and transfer the parallelized read commands;

the interface system configured to receive the parallelized read commands and apportion the parallelized read commands among the ones of the plurality of solid state memory subsystems, and transfer the parallelized read commands;

the ones of the plurality of solid state memory subsystems configured to receive associated ones of the parallelized read commands, and in response, retrieve read data portions and transfer the read portions;

the interface system configured to receive the read portions and transfer the read portions;

the storage processing system configured to receive the read portions, process the read portions against the storage allocation information to de-parallelize the read portions into merged read data, and transfer the merged read data.

3. The solid state storage device of claim 1, wherein the aggregated multi-channel interface comprises a plurality of physical links each comprising a physical communication layer;

and comprising;

the storage processing system configured to selectively merge or separate ones of the physical links into the aggregated multi-channel interface based on instructions received over a graphical configuration interface.

4. The solid state storage device of claim 1, wherein the parallelized data comprises portions of the data, and wherein the storage processing system is configured to determine ones of the plurality of solid state memory subsystems to allocate the portions among based on a storage address received with the data and the storage allocation information, wherein the storage allocation information comprises indicators of data allocations for each of the plurality of solid state memory subsystems.

5. The solid state storage device of claim 1, wherein each of the plurality of solid state memory subsystems comprises a physical drive encased in a common enclosure with the interface system and the storage processing system, and wherein ones of the plurality of solid state memory subsystems are presented as a virtual drive to the external host system.

6. The solid state storage device of claim 1, further comprising:

a configuration system configured to receive a configuration from a user of the solid state storage device, wherein the configuration indicates a quantity and arrangement of virtual volumes;

the storage processing system configured to apply the configuration to subdivide the plurality of solid state memory subsystems into a plurality of virtual volumes;

the interface system configured to present the plurality of virtual volumes as separate drive volumes to the host system;

wherein the write instruction comprises an indicator of one of the drive volumes on which to store the data; and

the interface system configured to parallelize the data among ones of the plurality of solid state memory subsystems which comprise the indicated one of the drive volume.

7. The solid state storage device of claim 6, wherein the configuration interface comprises a graphical user interface provided over at least a portion of the aggregated multi-channel interfaces configured to allow a user to alter the configuration of the solid state storage device.

8. The solid state storage device of claim 1, further comprising:

a power control system configured to receive backup power from a backup power source comprising a backup power source technology type, and detect interruptions in a primary power source and in response provide the backup power to the solid state storage device;

while providing the backup power, the power control system is configured to indicate power down information based on the backup power source technology type; and

the interface system configured to perform a soft power down operation to commit pending write instructions, associated data, and the storage allocation information to ones of the plurality of solid state memory subsystems based on the power down information.

9. The solid state storage device of claim 1, further comprising:

a utilization monitor configured to identify a utilization level of the storage processing system and transfer the utilization level;

clock rate optimization circuitry configured to determine a clock rate for ones of the storage processing system, interface system, and solid state memory subsystems based on the utilization level.

10. The solid state storage device of claim 1, further comprising:

integrated circuit chips comprising the interface system, storage processing system, and plurality of solid state memory subsystems disposed on surfaces of a plurality of printed circuit boards;

chassis structural elements configured to mate with and hold the plurality of printed circuit boards; and

wherein the chassis structural elements and the printed circuit boards are assembled to comprise an enclosure for the solid state memory device; and

wherein an outer surface of a first printed circuit board comprises a first outer surface of the enclosure and an outer surface of a second printed circuit board comprises a second outer surface of the enclosure.

11. A method of operating a solid state storage device, the method comprising:

in an interface system, communicating with an external host system over an aggregated multi-channel interface to receive data for storage by the solid state storage device;

in a storage processing system, communicating with the interface system to receive the data, processing the data against storage allocation information to parallelize the data among a plurality of solid state memory subsystems, and transferring the parallelized data;

in the interface system, receiving the parallelized data, apportioning the parallelized data among the plurality of solid state memory subsystems, and transferring the parallelized data for storage in the plurality of solid state memory subsystems;

wherein each of the plurality of solid state memory subsystems is configured to receive the associated portion of the parallelized data and store the associated portion on a solid state storage medium.

12. The method of claim 11, comprising:

in the interface system, communicating with the external host system over the aggregated multi-channel interface to receive a read instruction to retrieve existing data previously stored by the solid state storage device;

in the storage processing system, communicating with the interface system to receive the read instruction, processing the read instruction against the storage allocation information to determine parallelized read commands for ones of the plurality of solid state memory subsystems, and transferring the parallelized read commands;

in the interface system, receiving the parallelized read commands and apportioning the parallelized read commands among the ones of the plurality of solid state memory subsystems, and transferring the parallelized read commands;

in the ones of the plurality of solid state memory subsystems, receiving associated ones of the parallelized read commands, and in response, retrieving read data portions and transfer the read portions;

in the interface system, receiving the read portions and transferring the read portions;

in the storage processing system, receiving the read portions, processing the read portions against the storage allocation information to de-parallelize the read portions into merged read data, and transferring the merged read data.

13. The method of claim 11, wherein the aggregated multi-channel interface comprises a plurality of physical links each comprising a physical communication layer;

and further comprising;

the storage processing system selectively merging or separating ones of the physical links into the aggregated multi-channel interface based on instructions received over a graphical configuration interface.

14. The method of claim 11, wherein the parallelized data comprises portions of the data;

and

wherein processing the data against the storage allocation information to parallelize the data among the plurality of solid state memory subsystems comprises, in the storage processing system, determining ones of the plurality of solid state memory subsystems to allocate the portions among based on a storage address received with the data and the storage allocation information, wherein the storage allocation information comprises indicators of data allocations for each of the plurality of solid state memory subsystems.

15. The method of claim 11, wherein each of the plurality of solid state memory subsystems comprises a physical drive encased in a common enclosure with the interface system and the storage processing system, and wherein ones of the plurality of solid state memory subsystems are presented as a virtual drive to the external host system.

16. The method of claim 11, further comprising:

in a configuration system, receiving a configuration from a user of the solid state storage device, wherein the configuration indicates a quantity and arrangement of virtual volumes;

in the storage processing system, applying the configuration to subdivide the plurality of solid state memory subsystems into a plurality of virtual volumes;

in the interface system, presenting the plurality of virtual volumes as separate drive volumes to the host system;

wherein the write instruction comprises an indicator of one of the drive volumes on which to store the data; and

in the interface system, parallelizing the data among ones of the plurality of solid state memory subsystems which comprise the indicated one of the drive volume.

17. The method of claim 16, wherein the configuration interface comprises a graphical user interface provided over at least a portion of the aggregated multi-channel interfaces configured to allow a user to alter the configuration of the solid state storage device.

18. The method of claim 11, further comprising:

in a power control system, receiving backup power from a backup power source comprising a backup power source technology type, and detecting interruptions in a primary power source and in response providing the backup power to the solid state storage device;

while providing the backup power, in the power control system, indicating power down information based on the backup power source technology type; and

in the interface system, performing a soft power down operation to commit pending write instructions, associated data, and the storage allocation information to ones of the plurality of solid state memory subsystems based on the power down information.

19. The method of claim 11, further comprising:

in a utilization monitor, identifying a utilization level of the storage processing system and transferring the utilization level;

in clock rate optimization circuitry, determining a clock rate for ones of the storage processing system, interface system, and solid state memory subsystems based on the utilization level.

20. The method of claim 11, comprising:

wherein integrated circuit chips comprise the interface system, storage processing system, and plurality of solid state memory subsystems, and wherein the integrated circuit chips are each disposed on surfaces of a plurality of printed circuit boards;

wherein chassis structural elements are configured to mate with and hold the plurality of printed circuit boards; and

wherein the chassis structural elements and the printed circuit boards are assembled to comprise an enclosure for the solid state memory device; and

wherein an outer surface of a first printed circuit board comprises a first outer surface of the enclosure and an outer surface of a second printed circuit board comprises a second outer surface of the enclosure.