Three Dimensional Horizontal Diode Non-Volatile Memory Array and Method of Making Thereof

• US 20120091413A1
• Filed: 10/15/2010
• Published: 04/19/2012
• Est. Priority Date: 10/15/2010
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Nguyen, Natalie, Poon, Paul Wai Kie, Radigan, Steven J., Konevecki, Michael, Makala, Raghuveer S.
• Granted Patent: US 8,187,932 B2
• Time in Patent Office: Days
• US Class Current: 257/2
• CPC Class Codes: H01L 27/101 including resistors or capacitors only
• CPC Class Codes: H01L 27/1021 including diodes only
• CPC Class Codes: H10B 63/20 comprising selection components having two electrodes, e.g. diodes
• CPC Class Codes: H10B 63/845 the switching components being connected to a common vertical conductor

Abstract

A non-volatile memory device contains a three dimensional stack of horizontal diodes located in a trench in an insulating material, a plurality of storage elements, a plurality of word lines extending substantially vertically, and a plurality of bit lines. Each of the plurality of bit lines has a first portion that extends up along at least one side of the trench and a second portion that extends substantially horizontally through the three dimensional stack of the horizontal diodes. Each of the horizontal diodes is a steering element of a respective non-volatile memory cell of the non-volatile memory device, and each of the plurality of storage elements is located adjacent to a respective steering element.

Claims

1. -17. (canceled)

18. A method of making a non-volatile memory device, comprising:

forming a stack of alternating layers of a first material and a second material in a trench of an insulating material, wherein the first material comprises a semiconductor material and wherein the second material is insulating;

etching the stack to form at least one first rail-shaped opening in the stack, the at least one first rail-shaped opening extending in a first direction;

selectively etching the first material exposed in the at least one first rail-shaped opening to form first recesses in the first material such that the second material overhangs the first recesses;

doping a first outer portion of the first material exposed in the first recesses to form first conductivity type semiconductor portions of diodes;

forming a first conductive material in the first recesses and in the at least one first rail-shaped opening;

removing a portion of the first conductive material that is located in the at least one first rail-shaped opening to form separate horizontal bit lines in the first recesses;

forming a first insulating filling material in the at least one first rail-shaped opening;

etching the stack to separate the first material into a plurality of semiconductor features extending in a second direction different from the first direction;

forming a second insulating filling material between the plurality of semiconductor features;

etching the stack to form at least one second rail-shaped opening in the stack, the at least one second rail-shaped opening extending in the first direction;

doping a second outer portion of the first material exposed in the at least one second rail-shaped opening to form second conductivity type semiconductor portions of the diodes;

forming a storage material on a side wall of the at least one second rail-shaped opening in electrical contact of the second conductivity type semiconductor portions of the diodes such that at least a middle portion of the at least one second rail-shaped opening remains unfilled;

forming a second conductive material in the middle portion of the at least one second rail-shaped opening in electrical contact with the storage material; and

etching the second conductive material to form separate word lines extending substantially vertically.

19. The method of claim 18, wherein:

the step of selectively etching the first material forms the first recesses in the first material in at least two device levels at the same time;

the step of doping the first outer portion of the first material dopes the first outer portion of the first material in at least two device levels at the same time;

the step of doping the second outer portion of the first material dopes the second outer portion of the first material in at least two device levels at the same time; and

the step of forming storage material forms storage elements in more than two device levels at the same time.

20. The method of claim 18, further comprising:

forming a first barrier layer on the side wall of the at least one second rail-shaped opening prior to forming the storage material; and

forming a second barrier layer on the storage material layer in the middle portion of the at least one second rail-shaped opening;

wherein the step of forming the second conductive material in the middle portion of the at least one second rail-shaped opening forms the second conductive material on the second barrier layer.

21. The method of claim 18, wherein the step of etching the stack to form the at least one first rail-shaped opening comprises:

forming a first mask pattern over the stack;

forming a first spacer layer over the first mask pattern; and

etching the stack using a combination of the first mask pattern and the first spacer layer as a mask.

22. The method of claim 21, wherein the step of etching the stack to form the at least one second rail-shaped opening comprises:

forming a second mask pattern over the stack;

forming a second spacer layer over the second mask pattern; and

etching the stack using a combination of the second mask pattern and the second spacer layer as a mask.

23. The method of claim 18, wherein the step of etching the stack to form the at least one second rail-shaped opening comprises:

forming rail-shaped mask features over the stack, the rail-shaped mask features extending in the second direction;

forming spacers between the rail-shaped mask features;

removing the rail-shaped mask features; and

etching the stack using the spacers as a mask.

24. The method of claim 18, wherein the step of selectively etching the first material exposed in the at least one first rail-shaped opening to form first recesses in the first material comprises:

n-type doping an outer portion of the first material comprising an intrinsic silicon layer exposed in the at least one first rail-shaped opening; and

selectively removing the n-typed doped outer portion of the first material exposed in the at least one first rail-shaped opening.

25. The method of claim 18, wherein the step of selectively etching the first material exposed in the at least one first rail-shaped opening to form first recesses in the first material comprises:

oxidizing or nitriding an outer portion of the first material comprising a silicon layer exposed in the at least one first rail-shaped opening; and

selectively removing the oxidized or nitrided outer portion of the first material exposed in the at least one first rail-shaped opening.

26. The method of claim 18, wherein the storage material comprises at least one of antifuse, fuse, metal oxide resistivity switching material, complex metal oxide resistivity switching material, carbon nanotube switching material, graphene resistivity switching material, carbon resistivity switching material, phase change resistivity switching material, conductive bridge element, or polymer resistivity switching material.

27. The method of claim 18, wherein:

the first material comprises an intrinsic semiconductor material that is not intentionally doped; and

the diodes comprise p-i-n diodes.

28. The method of claim 18, further comprising forming a plurality of first electrical contacts to the plurality of bit lines and a plurality of second electrical contacts to the plurality of word lines.

29. The method of claim 28, wherein at least one of the plurality of the first electrical contacts is electrically connected to at least two of the plurality of bit lines located adjacent to each other in a same device level.

30. -32. (canceled)