SEMICONDUCTOR DEVICES INCLUDING ETCHING STOP FILMS

• US 20120091533A1
• Filed: 09/23/2011
• Published: 04/19/2012
• Est. Priority Date: 10/13/2010
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: KIM, Jong Pil, Jeong, Woncheol
• Granted Patent: US 9,209,087 B2
• Time in Patent Office: Days
• US Class Current: 257/369
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/53295 Stacked insulating layers
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor device may include a substrate including an NMOS region and a PMOS region. A gate structure can include a gate pattern and a spacer pattern, where the gate structure is on the substrate. A first etching stop film can be on the substrate in the NMOS region and a second etching stop film can be on the substrate in the PMOS region. A contact hole can penetrate the first and second etching stop films and a contact plug can be in the contact hole. A thickness of the first etching stop film can be greater than a thickness of the second etching stop film. Related methods are also disclosed.

Claims

1. A semiconductor device comprising:

a substrate including an NMOS region and a PMOS region;

a gate structure including a gate pattern and a spacer pattern on the substrate;

a first etching stop film on the substrate of the NMOS region;

a second etching stop film on the substrate of the PMOS region;

contact holes penetrating the first and second etching stop films; and

contact plugs formed in the contact holes,

wherein a thickness of the first etching stop film is greater than a thickness of the second etching stop film.

2. The semiconductor device of claim 1, further comprising:

a compression stress pattern in the substrate of the PMOS region; and

a semiconductor extension layer on the substrate of the NMOS region,

wherein the first etching stop film on the semiconductor extension layer and the second etching stop film on the compression stress pattern.

3. The semiconductor device of claim 2, wherein a top surface of the semiconductor extension layer is higher than a top surface of the compression stress pattern.

4. The semiconductor device of claim 3, wherein the contact plugs comprise:

a first contact plug penetrating the first etching stop film electrically connected to the semiconductor extension layer; and

a second contact plug penetrating the second etching stop film electrically connected to the compression stress pattern,

wherein a length of the second contact plug is greater than a length of the first contact plug.

5. The semiconductor device of claim 2, wherein the compression stress pattern comprises silicon-germanium.

6. The semiconductor device of claim 1, wherein the spacer pattern comprises a silicon nitride film and densities of the first and second etching stop films are greater than a density of the silicon nitride film.

7. The semiconductor device of claim 1, wherein the first and second etching stop films comprise at least one of silicon nitride and silicon carbide.

8. The semiconductor device of claim 1, wherein a top surface of the first etching stop film is higher than a top surface of the substrate and a bottom surface of the first etching stop film is lower than the top surface of the substrate.

9-20. -20. (canceled)