METHOD FOR FABRICATION OF A SEMICONDUCTOR DEVICE AND STRUCTURE

• US 20120091587A1
• Filed: 10/02/2011
• Published: 04/19/2012
• Est. Priority Date: 02/16/2010
• Status: Active Grant

• Current Assignee: Monolithic 3D, Inc.
• Original Assignee: Monolithic 3D, Inc.
• Inventors: Or-Bach, Zvi, Sekar, Deepak C., Cronquist, Brian
• Granted Patent: US 9,099,526 B2
• Time in Patent Office: Days
• US Class Current: 257/741
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/76232 of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls H01L21/76229 takes precedence
• CPC Class Codes: H01L 21/76254 with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 2221/68368 used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate
• CPC Class Codes: H01L 2221/68381 Details of chemical or physical process used for separating the auxiliary support from a device or wafer
• CPC Class Codes: H01L 2223/54426 for alignment
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2224/80006 being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/80009 Pre-treatment of the bonding area
• CPC Class Codes: H01L 2224/80047 by mechanical means, e.g. severing, pressing, stamping
• CPC Class Codes: H01L 2224/802 Applying energy for connecting
• CPC Class Codes: H01L 2224/80896 between electrically insulating surfaces, e.g. oxide or nitride layers
• CPC Class Codes: H01L 2224/9202 Forming additional connectors after the connecting process
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06589 Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/36 Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks H01L23/28, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence; heating H01L23/345
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/544 : Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/80 : Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 27/0207 : Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0688 : Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/1203 : the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1211 : combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01066 : Dysprosium [Dy]
• CPC Class Codes: H01L 2924/01072 : Hafnium [Hf]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01076 : Osmium [Os]
• CPC Class Codes: H01L 2924/01077 : Iridium [Ir]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/12032 : Schottky diode
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13062 : Junction field-effect transistor [JFET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1436 : Dynamic random-access memory [DRAM]
• CPC Class Codes: H01L 2924/1437 : Static random-access memory [SRAM]
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15788 : Glasses, e.g. amorphous oxides, nitrides or fluorides
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/351 : Thermal stress

Abstract

A 3D IC based system comprising a first semiconductor layer comprising first transistors, wherein the first transistors are interconnected by at least one metal layer comprising aluminum or copper; a second mono-crystallized semiconductor layer comprising second transistors and overlaying the metal layer; wherein the second mono-crystallized semiconductor layer thickness is less than 150 nm, and wherein at least one of the second transistors is an N-type transistor and at least one of the second transistors is a P-type transistor.

Claims

1. A 3D IC based system, comprising;

a first semiconductor layer comprising first transistors, wherein said first transistors are interconnected by at least one metal layer comprising aluminum or copper; and

a second mono-crystallized semiconductor layer comprising second transistors and overlaying said at least one metal layer,

wherein said second mono-crystallized semiconductor layer thickness is less than 150 nm, and

wherein at least one of said second transistors is an N-type transistor and at least one of said second transistors is a P-type transistor.

2. A system according to claim, 1 further comprising;

a plurality of connection paths between said second transistors and said first transistors,

wherein said plurality of connection paths comprise vias through said second mono-crystallized semiconductor layer,

wherein at least one of said vias is less than 150 nm in diameter.

3. A system according to claim 1, wherein;

said second transistor processing comprising at least one process step performed after second mono-crystallized semiconductor layer has been transferred to overlay said first semiconductor layer.

4. A system according to claim 1, wherein;

said system comprises a mobile computer.

5. A system according to claim 1, further comprising;

a heat spreader between said first semiconductor layer and said second mono-crystallized semiconductor layer.

6. A system according to claim 1, further comprising;

a plurality of connection paths between said second transistors and said first transistors,

wherein at least one of said connection paths has a contact to said second transistors, and

wherein said contact is also aligned to one of first alignment marks.

7. A system according to claim 1 wherein at least one of said second transistors is one of:

(i) a recessed-channel transistor (RCAT);

(ii) a junction-less transistor;

(iii) a replacement-gate transistor;

(iv) a thin-side-up transistor;

(v) a double gate transistor;

or

(vi) a horizontally oriented transistor.

8. A 3D IC based system, comprising;

a first semiconductor layer comprising first transistors, wherein said first transistors are interconnected by at least one metal layer comprising aluminum or copper;

a second mono-crystallized semiconductor layer comprising second transistors and overlaying said at least one metal layer; and

a plurality of connection paths between said second transistors and said first transistors comprise vias through said second mono-crystallized semiconductor layer, wherein;

said vias diameter is less than 150 nm

and wherein said second transistors are horizontally oriented transistors.

9. A system according to claim 8 wherein;

said second transistor processing comprising at least one process step performed after second mono-crystallized semiconductor layer has been transferred to overlay said first semiconductor layer.

10. A system according to claim 8 wherein;

said second mono-crystallized semiconductor layer thickness is less than 150 nm.

11. A system according to claim 8 wherein;

said system comprises a mobile computer.

12. A system according to claim 8 wherein;

said second transistors comprise a plurality of N-type transistors and P-type transistors.

13. A system according to claim 8 comprising;

a heat spreader between said first semiconductor layer and said second mono-crystallized semiconductor layer.

14. A system according to claim 8 wherein at least one of said second transistors is one of:

(i) a recessed-channel transistor (RCAT);

(ii) a junction-less transistor;

(iii) a replacement-gate transistor;

(iv) a thin-side-up transistor;

or

(v) a double gate transistor.

15. A 3D IC based system, comprising;

a first semiconductor layer comprising, first alignment marks and first transistors, wherein said first transistors are interconnected by at least one metal layer comprising aluminum or copper,

a second mono-crystallized semiconductor layer comprising second transistors and overlaying said at least one metal layer, and

wherein a plurality of connection paths between said second transistors and said first transistors,

wherein said second transistors are horizontally oriented transistors,

wherein at least one of said connection paths has a contact to said second transistors, and

wherein said contact is also aligned to one of first alignment marks.

16. A system according to claim 15, wherein;

said second mono-crystallized semiconductor layer thickness is less than 150 nm.

17. A system according to claim 15, wherein;

said system comprises a mobile computer.

18. A system according to claim 15, wherein;

said second transistors comprise a plurality of N-type transistors and P-type transistors.

19. A system according to claim 15, comprising;

a heat spreader between said first semiconductor layer and said second mono-crystallized semiconductor layer.

20. A system according to claim 15, wherein;

said second transistor processing comprises at least one process step performed after third semiconductor layer had been transferred to overlay said second mono-crystallized semiconductor layer.

21. A system according to claim 15, comprising;

a plurality of connection paths between said second transistors and said first transistors

wherein said connection paths comprise vias through said second mono-crystallized semiconductor layer,

wherein said via diameter is less than 150 nm.

22. A system according to claim 15 wherein at least one of said second transistors is one of:

(i) a recessed-channel transistor (RCAT);

(ii) a junction-less transistor;

(iii) a replacement-gate transistor;

(iv) a thin-side-up transistor;

or

(v) a double gate transistor.

23. A 3D IC based system, comprising;

a first semiconductor layer comprising, first alignment marks and first transistors, wherein said first transistors are interconnected by at least one metal layer comprising aluminum or copper,

a second mono-crystallized semiconductor layer comprising second transistors and overlaying said at least one metal layer, and

a reusable donor wafer,

wherein said second transistors comprise horizontally oriented transistors, and

wherein said second mono-crystallized semiconductor layer was transferred from said reusable donor wafer.

24. A system according to claim 23, wherein;

said second mono-crystallized semiconductor layer thickness is less than 150 nm.

25. A system according to claim 23, wherein;

said second transistors comprise a plurality of N-type transistors and P-type transistors.

26. A system according to claim 23, comprising;

a heat spreader between said first semiconductor layer and said second mono-crystallized semiconductor layer.

27. A system according to claim 23, wherein;

said second transistor processing comprises at least one process step performed after third semiconductor layer had been transferred to overlay said second mono-crystallized semiconductor layer.

28. A system according to claim 23, comprising;

A plurality of connection paths between said second transistors and said first transistors comprise vias through said second mono-crystallized semiconductor layer, wherein;

said vias diameter is less than 150 nm.

29. A system according to claim 23 wherein at least one of said second transistors is one of:

(i) a recessed-channel transistor (RCAT);

(ii) a junction-less transistor;

(iii) a replacement-gate transistor;

(iv) a thin-side-up transistor;

or

(v) a double gate transistor.

30. A system according to claim 23, wherein some of said second transistor'"'"'s contact alignment comprises at least one of said first alignment marks.