STRUCTURE AND METHOD FOR SIMULTANEOUSLY FORMING A THROUGH SILICON VIA AND A DEEP TRENCH STRUCTURE

• US 20120091593A1
• Filed: 10/14/2010
• Published: 04/19/2012
• Est. Priority Date: 10/14/2010
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Cheng, Kangguo, Farooq, Mukta G., Hsu, Louis L.
• Granted Patent: US 8,492,241 B2
• Time in Patent Office: Days
• US Class Current: 257/774
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: H01L 21/743 Making of internal connections, substrate contacts
• CPC Class Codes: H01L 21/763 Polycrystalline semiconductor regions H01L21/76264 takes precedence
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique

Abstract

A through silicon via (TSV) and a deep trench capacitor (DTCap) or a deep trench isolation (DTI) are simultaneously formed on the same substrate by a single mask and a single reactive ion etching (RIE). The TSV trench is wider and deeper that the DTCap or DTI trench. The TSV and DTCap or DTI are formed with different dielectric materials on the trench sidewalls. The TSV and DTCap or DTI are perfectly aligned.

Claims

1. A method of forming a device, comprising:

providing a substrate;

depositing a pad film on top of the substrate;

simultaneously forming a first trench and a second trench in the substrate, wherein the first trench is wider and deeper than the second trench;

depositing a node dielectric layer on the pad film and on a bottom and sidewalls of both the first trench and the second trench;

depositing a first material over the node dielectric layer to completely fill the second trench and partially fill the first trench;

removing all of the first material from the first trench and some of the first material from the second trench;

depositing a liner on sidewalls of the first trench;

depositing a conductive material to fill the first trench;

planarizing the conductive material;

thinning the substrate to the node dielectric layer at the bottom of the first trench; and

removing the node dielectric layer from the bottom of the first trench.

2. The method according to claim 1, wherein the first material is a conductive material.

3. The method according to claim 2, wherein the first trench is a through silicon via (TSV) and the second trench is a deep trench capacitor (DTCap) and the liner is thicker than the node dielectric layer.

4. The method according to claim 1, wherein the first material is an insulating material.

5. The method according to claim 4, wherein the first trench is a through silicon via (TSV) and the second trench is a deep trench isolation (DTI).

6. The method according to claim 1, wherein the first trench and the second trench are formed by using the pad film as a mask and performing a reactive ion etch (RIE).

7. A method of forming a device, comprising:

providing a substrate;

depositing a pad film on top of the substrate;

simultaneously forming a wide trench for a through silicon via (TSV) and a narrow trench for a deep trench capacitor (DTCap) in the substrate;

depositing a node dielectric layer on the pad film and on a bottom and sidewalls of both the wide trench and the narrow trench;

depositing a first conductive material over the node dielectric layer to completely fill the narrow trench and partially fill the wide trench;

removing all of the first conductive material from the wide trench and some of the first conductive material from the narrow trench;

depositing a liner on sidewalls of the wide trench;

depositing a second conductive material to fill the wide trench;

planarizing the second conductive material;

thinning the substrate to the node dielectric layer at a bottom of the wide trench; and

removing the node dielectric layer from the bottom of the wide trench.

8. The method according to claim 7, wherein the substrate is one of a bulk semiconductor and a semiconductor-on-insulator (SOI).

9. The method according to claim 7, wherein the pad film is deposited by chemical vapor deposition (CVD), atomic layer deposition (ALD), rapid thermal chemical vapor deposition (RTCVD) or plasma enhanced chemical vapor deposition (PECVD).

10. The method according to claim 7, wherein the node dielectric layer is deposited by chemical vapor deposition (CVD).

11. The method according to claim 10, wherein the node dielectric layer is selected from the group consisting of:

silicon nitride, silicon oxide, oxynitride and high-k dielectric.

12. The method according to claim 11, wherein the node dielectric layer has a thickness in a range from about 3 nm to 20 nm.

13. The method according to claim 7, wherein the first conductive material is selected from the group consisting of:

polycrystalline, amorphous silicon, germanium, silicon germanium, tungsten, titanium, tantalum, ruthenium, zirconium, cobalt, copper, aluminum, lead, platinum, tin, silver, gold, tantalum nitride, titanium nitride, tungsten silicide, tungsten nitride, ruthenium oxide, cobalt silicide, nickel silicide, carbon nanotube and conductive carbon.

14. The method according to claim 13, wherein the first conductive material has a thickness, t, greater than half the width, W2, of the narrow trench and less than half the width, W1, of the wide trench.

15. The method according to claim 7, wherein the liner is an oxide.

16. The method according to claim 15, wherein the liner has a thickness in a range from about 10 nm to 100 nm.

17. The method according to claim 7, wherein the second conductive material is one of a doped polysilicon and a metal or a combination of both.

18. The method according to claim 7, wherein the planarizing step comprises performing a chemical mechanical polishing (CMP).

19. A method of forming a device, comprising:

providing a substrate;

depositing a pad film on top of the substrate;

simultaneously forming a through silicon via (TSV) trench and a deep trench isolation (DTI) trench in the substrate;

depositing an insulating material to completely fill the DTI trench and partially fill the TSV trench;

removing insulting material from the TSV trench and the DTI trench, wherein a spacer liner is formed on sidewalls of the TSV trench;

depositing a conductive material to fill the TSV trench;

planarizing the conductive material; and

thinning the substrate to a bottom of the TSV trench.

20. The method according to claim 19, wherein the pad film is one of silicon nitride and silicon dioxide.

21. A device, comprising:

a substrate;

a first trench simultaneously formed with a second trench in the substrate, wherein the first trench is wider and deeper than the second trench;

a node dielectric layer deposited on a bottom and sidewalls of the first trench and on the sidewalls of the second trench;

a first material filling the second trench;

a liner deposited on the node dielectric layer in the first trench; and

a conductive material filling the first trench.

22. The device according to claim 21, wherein the first material is a conductive material, the first trench is a through silicon via (TSV) and the second trench is a deep trench capacitor (DTCap).

23. The device according to claim 21, wherein the first material is an insulating material, the first trench is a through silicon via (TSV) and the second trench is a deep trench isolation (DTI).

24. A design structure tangibly embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, the design structure comprising:

a first trench simultaneously formed with a second trench in a substrate, wherein the first trench is wider and deeper than the second trench;

a node dielectric layer deposited on a bottom and sidewalls of the first trench and on the sidewalls of the second trench;

a material filling the second trench;

a liner deposited on the node dielectric layer in the first trench; and

a conductive material filling the first trench.

25. The design structure of claim 24, wherein the design structure is synthesized into a netlist.