Method of Producing a Chip Package, and Chip Package

• US 20120091594A1
• Filed: 10/18/2011
• Published: 04/19/2012
• Est. Priority Date: 10/18/2010
• Status: Active Grant

• Current Assignee: Fraunhofer Gesellschaft Zur Foerderung Der Angewandten Forsching E.V.
• Original Assignee: Fraunhofer Gesellschaft Zur Foerderung Der Angewandten Forsching E.V.
• Inventors: LANDESBERGER, Christof, FAUL, Robert
• Granted Patent: US 8,563,358 B2
• Time in Patent Office: Days
• US Class Current: 257/774
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/06181 On opposite sides of the body
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/21 of an individual HDI interconnect
• CPC Class Codes: H01L 2224/2101 Structure
• CPC Class Codes: H01L 2224/211 Disposition
• CPC Class Codes: H01L 2224/2731 in liquid form
• CPC Class Codes: H01L 2224/27318 by dispensing droplets
• CPC Class Codes: H01L 2224/2732 Screen printing, i.e. using a stencil
• CPC Class Codes: H01L 2224/27436 Lamination of a preform, e.g. foil, sheet or layer
• CPC Class Codes: H01L 2224/2919 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/83132 using marks formed outside the semiconductor or solid-state body, i.e. "off-chip"
• CPC Class Codes: H01L 2224/83143 Passive alignment, i.e. self alignment, e.g. using surface energy, chemical reactions, thermal equilibrium
• CPC Class Codes: H01L 2224/83191 : wherein the layer connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/83192 : wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/8385 : using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
• CPC Class Codes: H01L 2224/83851 : being an anisotropic conductive adhesive
• CPC Class Codes: H01L 2224/83874 : Ultraviolet [UV] curing
• CPC Class Codes: H01L 2224/92244 : the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 23/3121 : a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/4985 : Flexible insulating substrates H01L23/49572 and H01L23/49855 take precedence
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 23/552 : Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 23/564 : Details not otherwise provided for, e.g. protection against moisture getters H01L23/26
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 : Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/27 : Manufacturing methods
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/0102 : Calcium [Ca]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01068 : Erbium [Er]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01077 : Iridium [Ir]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/0132 : Binary Alloys
• CPC Class Codes: H01L 2924/0133 : Ternary Alloys
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/0665 : Epoxy resin
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/15321 : being a ball array, e.g. BGA
• CPC Class Codes: H05K 1/185 : Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit semiconductor chips encapsulated by interconnect and support structures H01L23/5389, H01L24/00
• CPC Class Codes: H05K 2201/10674 : Flip chip

Abstract

A method of producing a chip package includes providing a substrate comprising a first recess having a recess bottom and recess side walls. A chip comprising a chip backside is introduced into the recess such that the chip does not protrude from the recess and such that a gap remains between the recess side walls and the chip, the chip backside being attached to the recess bottom. The gap is filled with a filler material.

Claims

1. Method of producing a chip package, comprising:

providing a substrate comprising a recess having a recess bottom and recess side walls in a first surface

introducing a chip, which has a chip backside, into the recess such that the chip does not protrude from the recess and that a gap remains between the recess side walls and the chip, the chip backside being attached to the recess bottom; and

filling the gap with a filler material,

wherein the substrate comprises a flexible one-layer or multi-layer film-roll substrate, wherein the chip comprises a flexible semiconductor chip having a thickness which ranges from 10 μ

m to 50 μ

m, and wherein the method is performed in a roll-to-roll method.

2. Method as claimed in claim 1, wherein the filling is performed while using doctor coating.

3. Method as claimed in claim 1, wherein the filling is performed while using a stencil printing method.

4. Method as claimed in claim 1, wherein the filling comprises introducing a liquid material into the gap and subsequent curing of the material.

5. Method as claimed in claim 1, which comprises introducing a liquid adhesive into the recess before the chip is introduced, so that the chip will position itself in a central area of the recess due to capillary forces.

6. Method as claimed in claim 1, wherein the substrate comprises a photopatternable layer, within which the recess is lithographically patterned.

7. Method as claimed in claim 1, wherein a contact area provided with a bump is provided on a chip frontside which is opposite the chip backside and which after the filling projects from the filler material.

8. Method as claimed in claim 7, further comprising etching so as to expose surfaces of the bumps.

9. Method as claimed in claim 1, wherein a frontside of the chip, which is opposite the backside of the chip, is coplanar with the first surface of the substrate, so that after the filling a contact area arranged on the frontside of the chip is exposed.

10. Method as claimed in claim 1, wherein a frontside of the chip, which is opposite the backside of the chip, is set back in relation to the first surface of the substrate, filling the gap comprising filling the recess and providing filler material on the frontside of the chip.

11. Method as claimed in claim 10, further comprising patterning the filler material arranged over the frontside of the chip so as to expose at least one contact area on the frontside of the chip.

12. Method as claimed in claim 11, wherein a photomask is used for exposing the at least one contact area, adjustment of the photomask being effected on the basis of edges and/or corners of the recess filled with the filler material.

13. Method as claimed in claim 1, wherein the substrate comprises at least two recesses, one chip of identical or different electrical or electronic function(s) being introduced into each of the recesses, respectively, such that it does not protrude from the recess and that a gap remains between the recess walls and the chip, the chip backside being attached to the recess bottom, wherein the gap in each recess is filled with a filler material, the method comprising producing a thin-film wiring metallization, which connects contact areas on the frontsides of the chips, on the first surface of the substrate.

14. Method as claimed in claim 1, further comprising producing a thin-film wiring metallization on the first surface of the substrate, wherein the thin film metallization is connected to at least one contact area on a frontside of the chip opposite to the backside of the chip.

15. Method as claimed in claim 14, further comprising producing a cover layer on the thin-film wiring metallization and on the first surface of the substrate, the cover layer leaving open at least one external contact area of the chip package.

16. Method as claimed in claim 15, further comprising producing a protective layer on the cover layer, the protective layer leaving open at least the external contact area of the chip package, and/or producing a protective layer on the backside of the substrate.

17. Method as claimed in claim 1, wherein the filler material is cured from a second surface of the substrate which is opposite the first surface, so that the chip acts as a shadow mask and parts of the filler material that are arranged on the frontside of the chip are not cured.

18. Method as claimed in claim 1, wherein the chip backside has a contact area arranged thereon which is glued, by means of a conductive adhesive, onto a conductive layer arranged on the recess bottom.

19. Method as claimed in claim 1, wherein the recess bottom and the chip backside are planar, a continuous planar adhesive layer being arranged between the recess bottom and the chip backside.

20. Method as claimed in claim 1, wherein the respective steps for several chip packages are performed in parallel on a film laminate, comprising a step of dicing the film laminate into the individual chip packages.

21. Method as claimed in claim 1, wherein a conductive layer is formed on the recess bottom.

22. Chip package comprising:

a substrate comprising a recess having a recess bottom and recess side walls in a surface thereof, wherein a conductive layer is arranged on the recess bottom; and

a chip having a planar chip backside which is attached to the planar recess bottom, comprising a chip frontside which is opposite the chip backside and does not protrude from the recess, a gap being arranged between the recess side walls and the chip which is filled with a filler material,

wherein the substrate comprises a flexible one-layer or multi-layer substrate, and wherein the chip comprises a flexible semiconductor chip having a thickness which ranges from 10 μ

m to 75 μ

m.

23. Chip package as claimed in claim 22, wherein a continuous planar adhesive layer is arranged between the chip backside and the recess bottom.

24. Chip package as claimed in claim 22 or 23, wherein the filler material is distinguishable from the material of the substrate.

25. Chip package as claimed in claim 22, wherein the substrate comprises a first layer and a second layer, the recess being formed by the first layer rather than by the second layer.

26. Chip package as claimed in claim 22, comprising:

at least one contact area arranged on the frontside of the chip; and

a wiring metallization on that surface of the substrate in which the recess is formed which connects the contact area to an external contact area of the chip package.

27. Chip package as claimed in claim 22, wherein the substrate comprises at least two recesses, one chip of identical or different electrical or electronic function(s) being introduced into each of the recesses, respectively, such that its frontside does not protrude from the recess and that a gap remains between the recess side walls and the chip, the chip backside being attached to the recess bottom, a thin-film wiring metallization, which connects contact areas on the frontsides of the chips, being provided on the first surface of the substrate.

28. Chip package as claimed in claim 26, comprising a cover layer which is arranged on that surface of the substrate which comprises the recess, and on the wiring metallization, and which leaves open at least one external contact area of the chip package.

29. Chip package as claimed in claim 28, further comprising a protective layer on the cover layer, the cover layer leaving open at least the external contact area of the chip package.

30. Chip package as claimed in claim 22, comprising:

a contact area arranged on the chip backside and connected to the conductive layer via a conductive adhesive.

31. Chip package as claimed in claim 22, wherein the conductive layer on the recess bottom is not electrically connected to a contact area of the chip.

32. Chip package as claimed in claim 31, wherein the chip does not have a contact area on the backside thereof.

33. Chip package as claimed in claim 30, wherein the substrate comprises a first layer, a second layer and a conductive intermediate layer between the first and second layers, the recessbeing formed in the first layer and extending to the conductive intermediate layer, the first layer comprising an opening extending, outside the recess, to the conductive intermediate layer and being filled with a conductive material.

34. Chip package as claimed in claim 22, wherein a chip frontside, which is opposite the chip backside, is coplanar with that surface of the substrate which comprises the recess.

35. Chip package as claimed in claim 22, wherein a chip frontside, which is opposite the chip backside, is set back in relation to that surface of the substrate which comprises the recess, filler material being arranged on the chip frontside, which filler material is patterned such that it does not cover at least one contact area on the chip frontside.

36. Chip package as claimed in claim 22, wherein an area of the substrate which comprises the recess is formed from a material of the following group:

benzocyclobutene, polyhydroxystyrene, Ormocer, patternable epoxy resins, polyethyleneterephthalate, polyimide, polyethylenenaphthalate, LCP (liquid crystal polymer), polycarbonate and polystyrene.

37. Chip package as claimed in claim 22, wherein the filler material comprises a material of the following group:

photoresist, benzocyclobutene, PHS (polyhydroxystyrene), polyimide, polydimethylsiloxane, Ormocer, adhesive, polymer, resin.

38. Chip package as claimed in claim 22, the top and bottom of which have plane-parallel configurations in that area where the chip is arranged, and in the areas adjacent thereto.