Method for Fabricating a Non-volatile Memory Device

• US 20120094451A1
• Filed: 12/27/2011
• Published: 04/19/2012
• Est. Priority Date: 10/10/2007
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: HONG, Young Ok, LEE, Myung Shik
• Granted Patent: US 8,377,782 B2
• Time in Patent Office: Days
• US Class Current: 438/258
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A method for fabricating a non-volatile memory device with asymmetric source/drain junctions, wherein a gate stack is formed on a semiconductor substrate, and impurity ions are implanted at a predetermined angle to form a source/drain junction in the semiconductor substrate. Thermal treatment of the semiconductor substrate forms an asymmetrically disposed source/drain junction between adjacent gate stacks.

Claims

1. A method for fabricating a non-volatile memory device comprising:

forming gate stacks on a semiconductor substrate;

implanting impurity ions at a predetermined tilt angle in the semiconductor substrate; and

performing a thermal treatment process to form an asymmetrically disposed source/drain junction between adjacent gate stacks.

2. The method of claim 1, wherein the gate stack comprises a tunneling layer, a charge trapping layer, a blocking layer, and a control gate.

3. The method of claim 2, wherein the charge trapping layer comprises a single layer or a multi layer.

4. The method of claim 1, wherein the predetermined tilt angle is approximately 4°

to approximately 7°

.

5. The method of claim 1, wherein the impurity ions are implanted on the semiconductor substrate with an energy of approximately 5 KeV to approximately 50 KeV and a dose of approximately 1×

10¹³ atom/cm² to approximately 1×

10¹⁴ atom/cm².

6. The method of claim 1, wherein the thermal treatment process is performed at a temperature between approximately 700°

C. and approximately 1000°

C.

7. The method of claim 1, wherein forming the gate stacks comprises:

forming a tunneling layer and a conductive layer for a floating gate on the semiconductor substrate;

patterning the conductive layer and exposing the semiconductor substrate on a device isolation region to form the floating gate;

etching an exposed area of the semiconductor substrate to form a trench;

filling the trench with an insulating layer to form a device isolation layer;

forming an interlayer insulating layer that surrounds the floating gate; and

forming a control gate on the interlayer insulating layer.