PERFORMANCE AND POWER OPTIMIZED COMPUTER SYSTEM ARCHITECTURES AND METHODS LEVERAGING POWER OPTIMIZED TREE FABRIC INTERCONNECT

• US 20120096211A1
• Filed: 09/15/2011
• Published: 04/19/2012
• Est. Priority Date: 10/30/2009
• Status: Active Grant

• Current Assignee: Calxeda Inc.
• Original Assignee: Calxeda Inc.
• Inventors: Davis, Mark Bradley, Borland, David James
• Granted Patent: US 9,876,735 B2
• Time in Patent Office: Days
• US Class Current: 710/314
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: H04L 47/125 by balancing the load, e.g. traffic engineering
• CPC Class Codes: H04L 49/10 characterised by the switching fabric construction
• CPC Class Codes: H04L 49/101 using crossbar or matrix
• CPC Class Codes: H04L 49/111 Switch interfaces, e.g. port details
• CPC Class Codes: H04L 49/351 for local area network [LAN], e.g. Ethernet switches
• CPC Class Codes: H04L 49/40 Constructional details, e.g. power supply, mechanical construction or backplane
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A performance and power optimized computer system architecture and method leveraging power optimized tree fabric interconnect are disclosed. One embodiment builds low power server clusters leveraging the fabric with tiled building blocks while another embodiment implements storage solutions or cooling solutions. Yet another embodiment uses the fabric to switch non-Ethernet packets, switch multiple protocols for network processors and other devices.

Claims

1. A computing device comprising:

a plurality of server nodes, wherein each server node includes a processor, a memory, an input/output circuit and a fabric switch that are interconnected to each other;

a fabric switch that interconnects the plurality of server nodes together by a plurality of fabric links; and

one or more Ethernet escapes from the fabric switch that form a power optimized server fabric.

2. The computing device of claim 1, wherein the plurality of server nodes are part of a server board.

3. The computing device of claim 2 further comprising an aggregate of a set of board, wherein each board has one or more server nodes, wherein each server node includes a processor, a memory, an input/output circuit and the set of boards are interconnected with the fabric switch to produce a larger server.

4. The computing device of claim 1, wherein the server nodes further comprise one or more fabric switches that switch of routing headers concatenated to Ethernet layer 2 packets.

5. The computing device of claim 1, wherein the fabric switch has a plurality of server node links wherein a speed of each server node link is set to optimize power.

6. The computing device of claim 1, wherein the fabric switch has a plurality of server node links wherein a speed of each server node link is dynamically adjustable to optimize power.

7. The computing device of claim 6, wherein each server node link speed is dynamically adjustable based on one of instantaneous utilization of the server node link and an average utilization of the server node link.

8. The computing device of claim 3, wherein one or more fabric links and one or more Ethernet escape use a PCIe connector to connect to the set of boards.

9. The computing device of claim 1 further comprising a passive backplane that provides a point-to-point server interconnect fabric.

10. The computing device of claim 1, wherein the plurality of server nodes form a tree having one or more levels and wherein the Ethernet escapes are at any level of the tree.

11. The computing device of claim 1, wherein each Ethernet escape is one of enabled and disabled to match bandwidth with optimized power usage.

12. The computing device of claim 1, wherein data between the server nodes traverses the fabric switch but not the Ethernet escapes.

13. The computing device of claim 4, wherein each server node has the computational components turned off to reduce power.

14. The computing device of claim 2 further comprising a plurality of server boards that form one of a rack and a backplane.

15. The computing device of claim 14 further comprising a plurality of shelves that compose a rack.

16. A computing device, comprising:

a storage device having a form factor;

a server node, wherein the server node includes a processor, a memory, an input/output circuit, a switch fabric and one or more SATA interfaces for the storage device, the server node having the same form factor as the storage device.

17. The computing device of claim 16 further comprising an array of storage devices and an array of server nodes interconnected to each other.

18. The computing device of claim 16, wherein the server node is within the storage device.

19. The computing device of claim 16, wherein the server node is connected to the storage device and the storage device is local storage for the server node.

20. The computing device of claim 16 further comprising a plurality of storage devices wherein each storage device is connected to one of the SATA interfaces so that the server node controls the plurality of storage devices.

21. The computing device of claim 16 further comprising a plurality of server nodes and a plurality of storage devices, wherein the plurality of server nodes are a switch fabric and control the plurality of storage devices.

22. The computing device of claim 16 further comprising one or more Ethernet escapes and a link and wherein each Ethernet escape and link has a PCIe connector.

23. A method for producing a high density computing system, the method comprising:

providing a server node having a processor, a memory, an input/output circuit, a switch fabric and one or more SATA interfaces; and

encapsulating the server node into a form factor of a hard disk drive.

24. The method of claim 23, wherein the switch fabric connects the server node to a network.

25. The method of claim 23 further comprising replacing the a backplane of the hard disk drive with a backplane suitable for creating at least one internal switching pathway.

26. A method for producing a high density computing system, the method comprising:

providing a standard form factor disk drive; and

integrating a server node having a processor, a memory, an input/output circuit, a switch fabric and one or more SATA interfaces into the standard form factor disk drive, wherein integrated compute capabilities are provided within the standard form factor disk drive.

27. A computing device, comprising:

a circuit board;

one or more dynamic memory chips mounted on the circuit board;

one or more computing chips mounted to the circuit board;

one or more flash memory chips mounted to the circuit board;

wherein the circuit board is vertically mounted so that the one or more flash memory chips below the one or more computing chips and the one or more dynamic memory chips are above the one or more computing chips;

a chimney cooler of the vertically mounted circuit board.

28. The computing device of claim 27 further comprising a plurality of vertically oriented circuit boards that are cooled by the chimney cooling.

29. The computing device of claim 27, wherein the chimney cooler is a fan at a bottom of the circuit board that cools the circuit board.

30. The computing device of claim 27, wherein the chimney cooler is a pneumatic air source and a vent pipe.

31. The computing device of claim 27, wherein the one or more dynamic memory chips in the vertically mounted circuit board are not directly above the one or more computing chips.

32. The computing device of claim 27, wherein the circuit board is a printed circuit board.

33. The computing device of claim 27, wherein the one or more dynamic memory chips, one or more computing chips and one or more flash memory chips are mounted diagonally on the circuit board.

34. A computing device comprising:

one or more processors;

a bus fabric connected to the one or more processors;

a fabric switch connected to the bus fabric that output data from the computing device to one or more ports; and

one or more routing header processors, wherein each routing header processor is used to route a particular transport stream so that the fabric switch handles different transport streams.

35. The computing device of claim 34, wherein the different transport streams include a server transport stream, a storage transport stream and a networking transport stream.

36. The computing device of claim 34 further comprising one or more Ethernet MAC controllers connected to the bus fabric and the fabric switch is connected to the one or more Ethernet MAC controllers that output data from the computing device to one or more ports and the one or more routing header processors is a PCIe header processor for routing PCIe data across the fabric switch.

37. The computing device of claim 36 further comprising a PCIe controller connected to the bus fabric, a PCIe routing header connected to the PCIe controller that are capable of connecting to a PCIe PHY.

38. The computing device of claim 34 further comprising a network processor connected to the switch fabric.

39. The computing device of claim 36 further comprising a foreign device connected to at least one port.

40. A computing device comprising:

one or more processors;

a bus fabric connected to the one or more processors;

a fabric switch connected to the bus fabric that output data from the computing device to one or more ports;

a bus protocol bridge connected between the bus fabric and the switch fabric; and

one or more routing header processors, wherein each routing header processor is used to route a particular transport stream so that the fabric switch handles different transport streams.

41. A method for switching different transport streams;

comprising;

providing one or more processors and a bus fabric connected to the one or more processors;

providing a fabric switch connected to the bus fabric that output data from the computing device to one or more ports; and

switching, using one or more routing header processors, a particular transport stream so that the fabric switch handles different transport streams.

42. The method of claim 41, wherein the different transport streams include a server transport stream, a storage transport stream and a networking transport stream.

43. The method of claim 41 further comprising routing PCIe data across the fabric switch.

44. A method of load balancing using a switch fabric, comprising:

providing a server node having one or more processors, a bus fabric connected to the one or more processors;

a fabric switch connected to the bus fabric that output data from the computing device to one or more ports and an IP virtual server connected to the fabric switch;

receiving an incoming request;

routing the incoming request to the IP virtual server connected to the fabric switch;

generating, using the IP virtual server connected to the fabric switch, a routing header to a specific node of the fabric;

forwarding the incoming request to the specific node; and

processing, using the specific node, the incoming request to provide load balancing.

45. A method of processing using a switch fabric, comprising:

providing a server node having one or more processors, a bus fabric connected to the one or more processors;

a fabric switch connected to the bus fabric that output data from the computing device to one or more ports and an OpenFlow device connected to the fabric switch;

receiving an incoming request;

routing the incoming request to the OpenFlow device connected to the fabric switch;

generating, using the OpenFlow device, a routing header to a specific node of the fabric;

forwarding the incoming request to the specific node;

processing, using the specific node, the incoming request to provide load balancing; and

sending the processed incoming request back to the OpenFlow device.

46. A computing device, comprising:

one or more processors;

a bus fabric connected to the one or more processors;

a fabric switch connected to the bus fabric that output data from the computing device to one or more ports;

a PCIe interface connected to the bus fabric; and

an external processor connected to the computing device using the PCIe interface.

47. A computing device, comprising:

a fabric switch that output data from the computing device to one or more ports;

an Ethernet port connected to the fabric switch; and

an external processor connected to the computing device using an Ethernet interface.