LOW-POWER AUDIO DECODING AND PLAYBACK USING CACHED IMAGES

• US 20120096223A1
• Filed: 02/25/2011
• Published: 04/19/2012
• Est. Priority Date: 10/15/2010
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Castelloe, Michael Warren
• Granted Patent: US 8,762,644 B2
• Time in Patent Office: Days
• US Class Current: 711/118
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: G06F 12/0875 with dedicated cache, e.g. instruction or stack
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A particular method includes loading one or more memory images into a multi-way cache. The memory images are associated with an audio decoder, and the multi-way cache is accessible to a processor. Each of the memory images is sized not to exceed a page size of the multi-way cache.

Claims

1. A method comprising:

loading one or more memory images associated with an audio decoder to a multi-way cache that is accessible to a processor, wherein each of the one or more memory images is sized to not exceed a page size of the multi-way cache.

2. The method of claim 1, wherein loading the one or more memory images to the multi-way cache enables audio decoding without the audio decoder causing any cache misses to occur at the multi-way cache.

3. The method of claim 2, wherein the audio decoding is performed after loading the one or more memory images into the multi-way cache without accessing a higher-level memory that is available to the processor.

4. The method of claim 1, wherein a size of each memory image is equal to the page size of the multi-way cache.

5. The method of claim 1, wherein the audio decoder is operable to decode one or more audio streams.

6. The method of claim 1, wherein the one or more memory images are each loaded from a memory to the multi-way cache and wherein the one or more memory images are each aligned in the memory to be loaded into a corresponding single page of the multi-way cache.

7. The method of claim 6, wherein the one or more memory images in the memory are accessible to enable audio decoding and low-power audio decoding when all of the one or more memory images are loaded into the multi-way cache.

8. The method of claim 6, wherein the memory includes one or more memory images associated with a second audio decoder.

9. The method of claim 6, wherein the memory includes at least one memory image that is common to a plurality of audio decoders.

10. The method of claim 6, wherein the memory includes a dynamic memory allocation region.

11. The method of claim 1, wherein the multi-way cache comprises a four-way cache.

12. The method of claim 1, wherein a first of the one or more memory images includes audio decoder program instructions, wherein a second of the one or more memory images corresponds to a dynamic memory allocation region, and wherein a third of the one or more memory images includes post-processing program instructions.

13. The method of claim 1, further comprising initiating a process to cause loading of an entire memory image of the one or more memory images into the multi-way cache.

14. The method of claim 13, wherein the process comprises a background thread of the processor.

15. The method of claim 13, wherein the process is initiated in response to detecting a start or a stop of an audio decoding process.

16. The method of claim 1, further comprising:

concurrently decoding a first audio stream at the audio decoder and a second audio stream at a second audio decoder;

detecting a termination of the second audio stream;

terminating the decoding of the second audio stream at the second decoder; and

decoding the first audio stream at the audio decoder after terminating the decoding of the second audio stream.

17. The method of claim 16, wherein the one or more memory images are loaded to the multi-way cache without an audible interruption in the first audio stream or in the second audio stream.

18. The method of claim 1, wherein the one or more memory images are loaded to the multi-way cache independently of intervention from an application processor.

19. The method of claim 1, further comprising:

decoding a first audio stream at the audio decoder without the audio decoder causing any cache misses to occur at the multi-way cache;

detecting a termination of the first audio stream and an initiation of a second audio stream to be decoded by a second audio decoder;

loading one or more memory images associated with the second audio decoder to the multi-way cache; and

decoding the second audio stream at the second audio decoder without the second audio decoder causing any cache misses to occur at the multi-way cache.

20. The method of claim 19, wherein the one or more memory images associated with the second audio decoder are loaded to the multi-way cache without an audible interruption in the first audio stream or in the second audio stream.

21. The method of claim 19, wherein the one or more memory images associated with the second audio decoder are loaded to the multi-way cache independently of intervention from an application processor.

22. The method of claim 1, further comprising accessing, at a memory integrated with the processor, program instructions that are common to multiple audio decoders.

23. The method of claim 1, wherein the processor comprises a digital signal processor.

24. The method of claim 1, further comprising:

receiving audio data;

wherein the one or more memory images are loaded in response to determining that the audio data corresponds to the audio decoder;

decoding the audio data at the audio decoder without causing a cache miss to occur at the multi-way cache; and

providing processed audio data to an output port of the processor.

25. The method of claim 24, further comprising:

applying one or more post-processing functions to decoded audio data to generate post-processed audio data, wherein the one or more post-processing functions are specific to the audio decoder; and

applying one or more common processing functions to the post-processed audio data to generate the processed audio data, wherein one or more common processing functions are common to a plurality of audio decoders.

26. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processor cause the processor to:

load one or more memory images associated with an audio decoder to a multi-way cache that is accessible to a processor, wherein each of the one or more memory images is sized to not exceed a page size of the multi-way cache.

27. The non-transitory computer-readable storage medium of claim 26, wherein loading the one or more memory images to the multi-way cache enables audio decoding without the audio decoder causing any cache misses to occur at the multi-way cache.

28. The non-transitory computer-readable storage medium of claim 26, wherein a size of each memory image is equal to the page size of the multi-way cache.

29. An electronic device, comprising:

a processor; and

a multi-way cache accessible to the processor,

wherein the processor is configured to load one or more memory images associated with an audio decoder into the multi-way cache, wherein each of the one or more memory images is sized not to exceed a page size of the multi-way cache.

30. The electronic device of claim 29, wherein loading the one or more memory images to the multi-way cache enables audio decoding without the audio decoder causing any cache misses to occur at the multi-way cache.

31. The electronic device of claim 29, further comprising:

a random access memory that includes the one or more memory images;

a low-power memory accessible to the processor;

an application processor configured to cause audio data to be retrieved from the random access memory and stored to the audio data at the low-power memory, wherein the audio decoder is configured to decode audio data retrieved from the low-power memory to generate decoded audio data;

post-processing circuitry configured to apply one or more post-processing operations to the decoded audio data generate post-processed audio data, wherein the one or more post-processing operations are specific to the audio decoder;

common processing circuitry configured to apply one or more common processing operations to the post-processed audio data to generate processed audio data, wherein the one or more common processing operations are common to a plurality of audio decoders; and

an output port configured to output the processed audio data.

32. An apparatus, comprising:

means for processing data; and

means for caching data in a plurality of cache ways,

wherein the means for caching is accessible to the means for processing, and

wherein the means for processing is configured to load one or more memory images associated with an audio decoder into the means for caching, wherein each of the one or more memory images is sized not to exceed a page size of the means for caching.

33. The apparatus of claim 32, wherein loading the one or more memory images to means for caching enables audio decoding without the audio decoder causing any cache misses to occur at the means for caching.

34. The apparatus of claim 32, wherein a size of each memory image is equal to the page size of the means for caching.

35. The apparatus of claim 32, wherein the audio decoder is an advanced audio coding (AAC)-type audio decoder, a motion picture experts group audio layer 3 (MP3)-type audio decoder, a speech audio decoder, a pulse-code modulation (PCM) audio decoder, or any combination thereof.

36. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processor, cause the processor to:

determine whether at least one buffer is available to satisfy a requested buffer size based on a bit mask, wherein a first bit of the bit mask indicates whether a buffer having a first buffer size is available and a second bit of the bit mask indicates whether a buffer having a second buffer size is available.

37. The non-transitory computer-readable storage medium of claim 36, wherein each bit location of the bit mask corresponds to a respective buffer size and wherein a bit value at a particular bit location indicates availability of a buffer having the respective buffer size corresponding to the particular bit location.

38. The non-transitory computer-readable storage medium of claim 36, further comprising instructions that, when executed by the processor, cause the processor to:

allocate a region of memory that is aligned to correspond to a single page of a multi-way cache and that has a size substantially equal to a size of the single page of the multi-way cache;

partition at least a portion of the allocated region of memory into a plurality of predetermined buffers that includes at least one buffer having the first buffer size and at least one buffer having the second buffer size;

populate one or more data structures with pointers to the predetermined buffers, wherein each pointer of a particular data structure points to a predetermined buffer of a particular size; and

set a bit mask to indicate available buffer sizes at the allocated region of memory.

39. The non-transitory computer-readable storage medium of claim 38, wherein the region of memory is cached at the multi-way cache and enables access by one or more audio decoders executing at a processor to enable audio decoding, wherein all dynamic memory allocation requests corresponding to the audio decoding are fulfilled from the region of memory cached at the multi-way cache.

40. The non-transitory computer-readable storage medium of claim 38, wherein each predetermined buffer has a size in accordance with a formula

size=2ⁿ+8 bytes,

where n is an integer greater than or equal to one.

41. The non-transitory computer-readable storage medium of claim 38, wherein a first four bytes of each predetermined buffer represent a corruption test word and wherein a second four bytes of each predetermined buffer represent a return pointer identifying one of the data structures.

42. The non-transitory computer-readable storage medium of claim 41, further comprising instructions that, when executed by the processor, cause the processor to:

receive a request indicating memory allocation of a requested size;

provide a pointer corresponding to a smallest available buffer satisfying the requested size;

receive a request to deallocate the provided buffer;

evaluate the corruption test word of the provided buffer to detect whether the provided buffer is corrupted; and

when the provided buffer is not corrupted, insert the pointer corresponding to the provided buffer into the data structure identified by the return pointer of the provided buffer.

43. A computer-implemented method, comprising:

at a processor, determining whether at least one buffer of a memory accessible to a processor is available to satisfy a requested buffer size based on a bit mask, wherein a first bit of the bit mask indicates whether a buffer having a first buffer size is available and a second bit of the bit mask indicates whether a buffer having a second buffer size is available.

44. The computer-implemented method of claim 43, further comprising:

allocating a region of the memory that is aligned to correspond to a single page of a multi-way cache and that has a size substantially equal to a size of the single page of the multi-way cache;

partitioning at least a portion of the allocated region of memory into a plurality of predetermined buffers that includes at least one buffer having the first buffer size and at least one buffer having the second buffer size;

populating one or more data structures with pointers to the predetermined buffers, wherein each pointer of a particular data structure points to a predetermined buffer of a particular size; and

setting a bit mask to indicate available buffer sizes at the allocated region of memory.