INFORMATION REPRESENTATION AND CODING FOR NONVOLATILE MEMORIES

• US 20120096234A1
• Filed: 09/20/2011
• Published: 04/19/2012
• Est. Priority Date: 09/20/2010
• Status: Active Grant

• Current Assignee: California Institute of Technology, Texas A&M University System
• Original Assignee: California Institute of Technology, Texas A&M University System
• Inventors: Jiang, Anxiao, Jehoshua, Bruck, Wang, Zhiying, Zhou, HongChao
• Granted Patent: US 8,780,620 B2
• Time in Patent Office: Days
• US Class Current: 711/170
• CPC Class Codes: G11C 11/5678 using amorphous/crystalline phase transition storage elements
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2213/52 Structure characterized by the electrode material, shape, etc.

Abstract

A memory device having a plurality of cells, each of which stores a value, where the values of the cells are mapped to discrete levels and the discrete levels represent data, is programmed by determining a maximum number of cell levels in the memory device, and determining the set of values that are associated with each of the cell levels. The maximum number of cell levels for the memory device is determined by an adaptive programming system connected to the memory device, based on a plurality of cell values attained by at least one cell of the memory device, in response to voltage applied by the adaptive programming system to the cells of the memory device. The adaptive programming system associates, for each of the cell levels, a different set of cell values of the plurality of cell values attained by the cells to which voltage is applied. This technique increases the number of cell levels that can be configured in a memory device as compared with conventional techniques, and increases the number of data values that can be programmed into the cells of a memory device.

Claims

1. A method of configuring a memory device having a plurality of cells, each of which stores a value, where the values of the cells are mapped to discrete levels and the discrete levels represent data, the method comprising:

determining a maximum number of cell levels in the memory device;

determining the set of values that are associated with each of the cell levels;

wherein the maximum number of cell levels for the memory device is determined by an adaptive programmer system connected to the memory device, based on a plurality of cell values attained by at least one cell of the memory device, in response to voltage applied by the adaptive programmer system to the cells of the memory device, such that the adaptive programmer system associates, for each of the cell levels, a different set of cell values of the plurality of cell values attained by the cells to which voltage is applied.

2. The method as in claim 1, wherein the memory device includes a set of cells with programmable voltage values, where the value of a cell refers to the voltage value of the cell, and a level refers to a range of values, wherein the ranges of values corresponding to different levels do not overlap.

3. The method as in claim 2, wherein determining a maximum number of cell levels and determining the set of values belonging to a level in the memory device by the adaptive programmer system comprises:

setting the maximum cell value for an initial level to be the maximum cell value of all or a group of cells in the memory device, and setting the set of cell values that belong to the initial level to be all values that are less than or equal to the above mentioned maximum cell value;

setting the minimum cell value for a next cell level to be the maximum cell value of the current cell level plus a safety gap increment that provides a spacing between cell levels that is beyond an expected noise level in the memory device circuitry;

applying a predetermined voltage for a predetermined time to at least one cell of the memory device;

detecting the value of a cell of the memory device, and comparing it to the minimum cell value of the next cell level;

repeating the applying, detecting, and comparing for a predetermined group of the cells in the memory device, until the values of all the cells in the predetermined group are greater than or equal to the minimum value of the next cell level;

setting the maximum cell value for the next level to be the maximum value of the cells in the predetermined group; and

setting the set of cell values that belong to the next level to be all the values between the minimum cell value and the maximum cell value for the next level;

setting the next cell level as a new current cell level, and setting the minimum cell value for the next cell level to be the maximum cell value of the current cell level plus a safety gap increment that provides a spacing between cell levels that is beyond an expected noise level in the memory device circuitry;

repeating the applying, detecting, and comparing for a predetermined group of the cells in the memory device, until the values of all the cells in the predetermined group are greater than or equal to the minimum value of the next cell level;

setting the maximum cell value for the next level to be the maximum value of the cells in the predetermined group; and

setting the set of cell values that belong to the next level to be all the values between the minimum cell value and the maximum cell value for the next level;

repeating the applying, detecting, comparing, and setting to program next levels, until one of the cells reaches a maximum possible value to which a cell can be set.

4. The method as in claim 3, wherein the cells in the same level x, where x>

=0, satisfy the following additional constraint;

let Y be a real number that is smaller than the safety gap increment between level x and level x+1;

sort the values of the cells in level x as v1<

=v2<

=v3<

= . . . <

=vk, where k is the number of cells in level x;

then the cell values need to satisfy the constraint that v2−

v1<

=Y, v3−

v2<

=Y, v4−

v3<

=Y, . . . , vk−

v(k−

1)<

=Y.

5. The method as in claim 3, wherein for two adjacent levels, level x and level x+1, where x>

=0, an additional cell called a Reference Cell is programmed such that its value is greater than the maximum cell value of level x and is smaller than the minimum cell value of level x+1

6. The method as in claim 1, wherein the memory device includes a set of cells with programmable electrical resistance values, where the value of a cell refers to the resistance of the cell or the logarithm of the resistance of the cell, and a level refers to a range of values, wherein the ranges of values corresponding to different levels do not overlap.

7. The method as in claim 6, wherein determining a maximum number of cell levels and determining the set of values belonging to a level in the memory device by the adaptive programmer system comprises:

setting the maximum cell value for an initial level to be the maximum cell value of all or a group of cells in the memory device, and setting the set of cell values that belong to the initial level to be all values that are less than or equal to the maximum cell value;

setting the minimum cell value for a next cell level to be the maximum cell value of the current cell level plus a safety gap increment that provides a spacing between cell levels that is beyond an expected noise level in the memory device circuitry;

applying a predetermined voltage for a predetermined time to at least one cell of the memory device;

detecting the value of a cell of the memory device, and comparing it to the minimum cell value of the next cell level;

repeating the applying, detecting, and comparing for a predetermined group of the cells in the memory device, until the values of all the cells in the predetermined group are greater than or equal to the minimum value of the next cell level;

setting the maximum cell value for the next level to be the maximum value of the cells in the predetermined group; and

setting the set of cell values that belong to the next level to be all the values between the minimum cell value and the maximum cell value for the next level;

setting the next level as a new current cell level, and setting the minimum cell value for a next cell level to be the maximum cell value of the current cell level plus a safety gap increment that provides a spacing between cell levels that is beyond an expected noise level in the memory device circuitry;

repeating the applying, detecting, and comparing for a predetermined group of the cells in the memory device, until the values of all the cells in the predetermined group are greater than or equal to the minimum value of the next cell level;

setting the maximum cell value for the next level to be the maximum value of the cells in the predetermined group; and

setting the set of cell values that belong to the next level to be all the values between the minimum cell value and the maximum cell value for the next level;

repeating the applying, detecting, comparing, and setting to program next levels, until one of the cells reaches a maximum possible value to which a cell can be set.

8. The method as in claim 7, wherein the cells in the same level x, where x>

=0, satisfy the following additional constraint;

let Y be a real number that is smaller than the safety gap increment between level x and level x+1;

sort the values of the cells in level x as v1<

=v2<

=v3<

= . . . <

=vk, where k is the number of cells in level x;

then the cell values need to satisfy the constraint that v2−

v1<

=Y, v3−

v2<

=Y, v4−

v3<

=Y, . . . , vk−

v(k−

1)<

=Y.

9. The method as in claim 7, wherein for two adjacent levels, level x and level x+1, where x>

=0, an additional cell called a Reference Cell is programmed such that its value is greater than the maximum cell value of level x and is smaller than the minimum cell value of level x+1.

10. The method as in claim 1, wherein the memory device includes a set of patterned cells, where each cell realizes a graph that contains at least two vertices, where every vertex has two programmable states denoted by “

ON” and

“

OFF” and

two vertices are called “

connected”

if and only if there is a path in the graph with the two vertices as endpoints that consists of only “

ON”

vertices, and wherein the value of a cell refers to the state of connectivity between the vertices of the graph realized in the cell, and a level refers to a set of values, and wherein the sets of values corresponding to different levels do not overlap.

11. The method as in claim 10, wherein determining a maximum number of cell levels and determining the set of values belonging to a level in the memory device by the adaptive programmer system comprises:

setting the set of cell values that belong to the initial level to be the unique state of connectivity where all vertices are OFF and no two vertices are connected in the graph;

setting the minimum cell value for a next cell level to be a state of connectivity where a first and a second adjacent vertices are ON and the other vertices are OFF in the graph;

applying a predetermined voltage for a predetermined time to at least one cell of the memory device;

detecting the connectivity between the first and the second vertices in the graph of a cell of the memory device;

repeating the applying and detecting for a predetermined group of the cells in the memory device, until for every cell in the predetermined group, the set of ON vertices in the graph include the first and the second vertices;

setting the set of cell values that belong to the next level to be all the values attained by the cells in the above predetermined group;

setting the next level as a new current cell level, and setting the minimum cell value for the next cell level to be a cell value that does not belong to the previously programmed cell levels;

repeating the applying and detecting for a predetermined group of the cells in the memory device, until for every cell in the predetermined group, its value does not belong to any of the previously programmed cell levels and its ON vertices in the graph include all those vertices that need to be ON in the minimum cell value of the next cell level;

setting the set of cell values that belong to the next level to be all the values attained by the cells in the predetermined group;

repeating the applying, detecting, and setting to program next levels, until one of the cells reaches the state where all the vertices in the graph are ON;

generating a configuration data set with the determined maximum number of cell levels and the set of cell values for each cell level for the memory device.

12. The method as in claim 11, wherein a cell is a PCM cell and a vertex in a cell is a domain whose state is controlled by a bottom electrode, where a domain has an crystalline state that represents the ON state and an amorphous state that represents the OFF state.

13. The method as in claim 10, wherein a patterned cell includes a phase-change memory (PCM) cell with at least two bottom electrodes and one top electrode, wherein every bottom electrode controls the ON state, corresponding to the crystalline state, and OFF state, corresponding to the amorphous state of a domain in the cell, wherein a domain represents a vertex in the corresponding graph, and two vertices have an edge between them in the graph if the electrodes of the two corresponding domains have a physical distance less than a predetermined parameter.

14. The method as in claim 1, wherein the value of a cell is determined by the adaptive programmer system in response to operations comprising:

applying a voltage by the adaptive programmer system to at least one cell of the memory device and determining a cell value attained by the cell in response to the voltage;

repeating the applying the voltage and determining the cell value until the cell value is at least equal to a target value;

wherein the adaptive programmer system establishes a cell level upon completing the applying and repeating for a subgroup of the cells in the memory device.

15. The method as in claim 1, further comprising generating a configuration data set for the memory device that defines a coding scheme that maps codewords to data comprising a sequence of binary bits, wherein the codewords of the coding scheme are defined by the set of cell levels determined for the memory device.

16. The method as in claim 15, wherein the codewords include codewords that have only level 0 and level 1, comprising 2-level codewords, or include codewords that have only level 0, level 1, and level 2 codewords, comprising 3-level codewords, and generally for a q-level codeword, include codewords that have only level 0, level 1, . . . , up to level q−

1, wherein q is an integral parameter that upper bounds the maximum number of levels that cells can possibly have.

17. The method as in claim 16, wherein for an x-level codeword and a y-level codeword with x<

y, if for every cell in the cell group, its level in the x-level codeword is less than or equal to its level in the y-level codeword, then the data encoded by the x-level codeword is a subset of the data encoded by the y-level codeword.

18. The method as in claim 17, wherein the data encoded by the x-level codeword is a prefix of the data encoded by the y-level codeword.

19. The method as in claim 17, wherein the q-level codewords are constant-weight codewords, namely, for x=0, 1, . . . , q−

1, all the q-level codewords have the same number of cells in level x.

20. The method as in claim 16, wherein n cells in the memory device store n bits of data, with each cell storing one bit of data conform to the following:

Let (L1, L2, . . . , Ln) denote the levels of an x-level codeword, where 2<

=x<

=q and each level Li (for 1<

=i<

=n) is in the set {0, 1, . . . , x−

1};

let (B1, B2, . . . , Bn) denote the n bits encoded by the codeword (L1, L2, . . . , Ln), then the mapping is that for 1<

=i<

=n, Bi=Li mod 2.

21. The method as in claim 16, wherein n cells in the memory device store n bits of data, with each cell storing one bit of data conforming to the following:

Let (L1, L2, . . . , Ln) denote the levels of an x-level codeword, where 2<

=x<

=q and each level Li (for 1<

=i<

=n) is in the set {0, 1, . . . , x−

1};

let (B1, B2, . . . , Bn) denote the n bits encoded by the codeword (L1, L2, . . . , Ln), then the mapping is that for 1<

=i<

=n, Bi=(Li+1) mod 2.

22. The method as in claim 16, wherein n cells in the memory device store nk bits of data, with each cell storing k bits of data conforming to the following:

Let (L1, L2, . . . , Ln) denote the levels of an x-level codeword, where 2<

=x<

=q and each level Li (for 1<

=i<

=n) is in the set {0, 1, . . . , x−

1};

given 1<

=i<

=n, let (B1, B2, . . . , Bk) denote the k bits encoded by the ith cell of level Li, then the mapping from Li to (B1, B2, . . . , Bk) satisfies the following constraints;

for any 0<

=y<

z<

=(2̂

k)−

1, the value of (B1, B2, . . . , Bk) for Li=y is different from the value of (B1, B2, . . . , Bk) for Li=z; and

for any 0<

=z<

=q−

1, the value of (B1, B2, . . . , Bk) for Li=z is the same as the value of (B1, B2, . . . , Bk) for Li=z mod 2̂

k.

23. The method as in claim 16, wherein for n cells in the memory device, each of them stores a data symbol from the set {0, 1, . . . , Y−

1} for some integer Y, with a method of mapping that comprises;

For 1<

=i<

=n, let Lidenote the level of the ith cell, and let Si denote the data symbol stored by the ith cell, then the mapping from Li to Si satisfies the following constraints;

for any 0<

=y<

z<

=Y−

1, the value of Si for Li=y is different from the value of Si for Li=z;

for any 0<

=z<

=q−

1, the value of Si for Li=z is the same as the value of Si for Li=z mod Y.

24. The method as in claim 16, wherein for n cells in the memory device, they cells store a data symbol from the set {0, 1, . . . , (Ŷ

n)−

1} for some integer Y>

=2, with a method of mapping that comprises;

Let (L1, L2, . . . , Ln) denote the levels of the n cells, and let S denote the data symbol stored by the n cells, then the mapping from the codeword (L1, L2, . . . , Ln) to S satisfies the following constraints;

for any two different codewords, where the first codeword is an x-level codeword with x<

=Y and the second codeword is a y-level codeword with y<

=Y, the value of S for the first codeword is different from the value of S for the second codeword;

the value of S for a codeword (L1, L2, . . . , Ln) is the same as the value of S for the codeword (L1 mod Y, L2 mod Y, . . . , Ln mod Y).

25. The method as in claim 15, further comprising:

storing the configuration data set from the adaptive programming system into the memory device.

26. An adaptive programmer system comprising:

a memory; and

a processor controller that executes program instructions stored in the memory to perform a process comprising

determining a maximum number of cell levels in a memory device having a plurality of cells, each of which stores a value, where the values of the cells are mapped to discrete levels and the discrete levels represent data, and

determining the set of values that are associated with each of the cell levels;

wherein the maximum number of cell levels for the memory device is determined by the adaptive programmer system when connected to the memory device, based on a plurality of cell values attained by at least one cell of the memory device, in response to voltage applied by the adaptive programmer system to the cells of the memory device, such that the adaptive programmer system associates, for each of the cell levels, a different set of cell values of the plurality of cell values attained by the cells to which voltage is applied.

27. The system as in claim 26, wherein the memory device includes a set of cells with programmable voltage values, where the value of a cell refers to the voltage value of the cell, and a level refers to a range of values, wherein the ranges of values corresponding to different levels do not overlap.

28. The system as in claim 27, wherein the adaptive programmer system determines a maximum number of cell levels and determining the set of values belonging to a level in the memory device by:

setting the maximum cell value for an initial level to be the maximum cell value of all or a group of cells in the memory device, and setting the set of cell values that belong to the initial level to be all values that are less than or equal to the above mentioned maximum cell value;

setting the minimum cell value for a next cell level to be the maximum cell value of the current cell level plus a safety gap increment that provides a spacing between cell levels that is beyond an expected noise level in the memory device circuitry;

applying a predetermined voltage for a predetermined time to at least one cell of the memory device;

detecting the value of a cell of the memory device, and comparing it to the minimum cell value of the next cell level;

repeating the applying, detecting, and comparing for a predetermined group of the cells in the memory device, until the values of all the cells in the predetermined group are greater than or equal to the minimum value of the next cell level;

setting the maximum cell value for the next level to be the maximum value of the cells in the predetermined group; and

setting the set of cell values that belong to the next level to be all the values between the minimum cell value and the maximum cell value for the next level;

setting the next cell level as a new current cell level, and setting the minimum cell value for the next cell level to be the maximum cell value of the current cell level plus a safety gap increment that provides a spacing between cell levels that is beyond an expected noise level in the memory device circuitry;

repeating the applying, detecting, and comparing for a predetermined group of the cells in the memory device, until the values of all the cells in the predetermined group are greater than or equal to the minimum value of the next cell level;

setting the maximum cell value for the next level to be the maximum value of the cells in the predetermined group; and

setting the set of cell values that belong to the next level to be all the values between the minimum cell value and the maximum cell value for the next level;

repeating the applying, detecting, comparing, and setting to program next levels, until one of the cells reaches a maximum possible value to which a cell can be set.

29. The system as in claim 28, wherein the cells in the same level x, where x>

=0, satisfy the following additional constraint;

let Y be a real number that is smaller than the safety gap increment between level x and level x+1;

sort the values of the cells in level x as v1<

=v2<

=v3<

= . . . <

=vk, where k is the number of cells in level x;

then the cell values need to satisfy the constraint that v2−

v1<

=Y, v3−

v2<

=Y, v4−

v3<

=Y, . . . , vk−

v(k−

1)<

=Y.

30. The system as in claim 28, wherein for two adjacent levels, level x and level x+1, where x>

=0, an additional cell called a Reference Cell is programmed such that its value is greater than the maximum cell value of level x and is smaller than the minimum cell value of level x+1

31. The system as in claim 26, wherein the memory device includes a set of cells with programmable electrical resistance values, where the value of a cell refers to the resistance of the cell or the logarithm of the resistance of the cell, and a level refers to a range of values, wherein the ranges of values corresponding to different levels do not overlap.

32. The system as in claim 31, wherein the adaptive programmer system determines a maximum number of cell levels and determining the set of values belonging to a level in the memory device by:

setting the maximum cell value for an initial level to be the maximum cell value of all or a group of cells in the memory device, and setting the set of cell values that belong to the initial level to be all values that are less than or equal to the maximum cell value;

setting the minimum cell value for a next cell level to be the maximum cell value of the current cell level plus a safety gap increment that provides a spacing between cell levels that is beyond an expected noise level in the memory device circuitry;

applying a predetermined voltage for a predetermined time to at least one cell of the memory device;

detecting the value of a cell of the memory device, and comparing it to the minimum cell value of the next cell level;

repeating the applying, detecting, and comparing for a predetermined group of the cells in the memory device, until the values of all the cells in the predetermined group are greater than or equal to the minimum value of the next cell level;

setting the maximum cell value for the next level to be the maximum value of the cells in the predetermined group; and

setting the set of cell values that belong to the next level to be all the values between the minimum cell value and the maximum cell value for the next level;

setting the next level as a new current cell level, and setting the minimum cell value for a next cell level to be the maximum cell value of the current cell level plus a safety gap increment that provides a spacing between cell levels that is beyond an expected noise level in the memory device circuitry;

repeating the applying, detecting, and comparing for a predetermined group of the cells in the memory device, until the values of all the cells in the predetermined group are greater than or equal to the minimum value of the next cell level;

setting the maximum cell value for the next level to be the maximum value of the cells in the predetermined group; and

setting the set of cell values that belong to the next level to be all the values between the minimum cell value and the maximum cell value for the next level;

repeating the applying, detecting, comparing, and setting to program next levels, until one of the cells reaches a maximum possible value to which a cell can be set.

33. The system as in claim 32, wherein the cells in the same level x, where x>

=0, satisfy the following additional constraint;

let Y be a real number that is smaller than the safety gap increment between level x and level x+1;

sort the values of the cells in level x as v1<

=v2<

=v3<

= . . . <

=vk, where k is the number of cells in level x;

then the cell values need to satisfy the constraint that v2−

v1<

=Y, v3−

v2<

=Y, v4−

v3<

=Y, . . . , vk−

v(k−

1)<

=Y.

34. The system as in claim 32, wherein for two adjacent levels, level x and level x+1, where x>

=0, an additional cell called a Reference Cell is programmed such that its value is greater than the maximum cell value of level x and is smaller than the minimum cell value of level x+1.

35. The system as in claim 26, wherein the memory device includes a set of patterned cells, where each cell realizes a graph that contains at least two vertices, where every vertex has two programmable states denoted by “

ON” and

“

OFF” and

two vertices are called “

connected”

if and only if there is a path in the graph with the two vertices as endpoints that consists of only “

ON”

vertices, and wherein the value of a cell refers to the state of connectivity between the vertices of the graph realized in the cell, and a level refers to a set of values, and wherein the sets of values corresponding to different levels do not overlap.

36. The system as in claim 35, wherein the adaptive programmer system determines a maximum number of cell levels and determining the set of values belonging to a level in the memory device by:

setting the set of cell values that belong to the initial level to be the unique state of connectivity where all vertices are OFF and no two vertices are connected in the graph;

setting the minimum cell value for a next cell level to be a state of connectivity where a first and a second adjacent vertices are ON and the other vertices are OFF in the graph;

applying a predetermined voltage for a predetermined time to at least one cell of the memory device;

detecting the connectivity between the first and the second vertices in the graph of a cell of the memory device;

repeating the applying and detecting for a predetermined group of the cells in the memory device, until for every cell in the predetermined group, the set of ON vertices in the graph include the first and the second vertices;

setting the set of cell values that belong to the next level to be all the values attained by the cells in the above predetermined group;

setting the next level as a new current cell level, and setting the minimum cell value for the next cell level to be a cell value that does not belong to the previously programmed cell levels;

repeating the applying and detecting for a predetermined group of the cells in the memory device, until for every cell in the predetermined group, its value does not belong to any of the previously programmed cell levels and its ON vertices in the graph include all those vertices that need to be ON in the minimum cell value of the next cell level;

setting the set of cell values that belong to the next level to be all the values attained by the cells in the predetermined group;

repeating the applying, detecting, and setting to program next levels, until one of the cells reaches the state where all the vertices in the graph are ON;

generating a configuration data set with the determined maximum number of cell levels and the set of cell values for each cell level for the memory device.

37. The system as in claim 36, wherein a cell is a PCM cell and a vertex in a cell is a domain whose state is controlled by a bottom electrode, where a domain has an crystalline state that represents the ON state and an amorphous state that represents the OFF state.

38. The system as in claim 35, wherein a patterned cell includes a phase-change memory (PCM) cell with at least two bottom electrodes and one top electrode, wherein every bottom electrode controls the ON state, corresponding to the crystalline state, and OFF state, corresponding to the amorphous state of a domain in the cell, wherein a domain represents a vertex in the corresponding graph, and two vertices have an edge between them in the graph if the electrodes of the two corresponding domains have a physical distance less than a predetermined parameter.

39. The system as in claim 26, wherein the value of a cell is determined by the adaptive programmer system in response to operations comprising:

applying a voltage by the adaptive programmer system to at least one cell of the memory device and determining a cell value attained by the cell in response to the voltage;

repeating the applying the voltage and determining the cell value until the cell value is at least equal to a target value;

wherein the adaptive programmer system establishes a cell level upon completing the applying and repeating for a subgroup of the cells in the memory device.

40. The system as in claim 26, wherein the adaptive programmer system further generates a configuration data set for the memory device that defines a coding scheme that maps codewords to data comprising a sequence of binary bits, wherein the codewords of the coding scheme are defined by the set of cell levels determined for the memory device.

41. The system as in claim 40, wherein the codewords include codewords that have only level 0 and level 1, comprising 2-level codewords, or include codewords that have only level 0, level 1, and level 2 codewords, comprising 3-level codewords, and generally for a q-level codeword, include codewords that have only level 0, level 1, . . . , up to level q−

1, wherein q is an integral parameter that upper bounds the maximum number of levels that cells can possibly have.

42. The system as in claim 41, wherein for an x-level codeword and a y-level codeword with x<

y, if for every cell in the cell group, its level in the x-level codeword is less than or equal to its level in the y-level codeword, then the data encoded by the x-level codeword is a subset of the data encoded by the y-level codeword.

43. The system as in claim 42, wherein the data encoded by the x-level codeword is a prefix of the data encoded by the y-level codeword.

44. The system as in claim 42, wherein the q-level codewords are constant-weight codewords, namely, for x=0, 1, . . . , q−

1, all the q-level codewords have the same number of cells in level x.

45. The system as in claim 41, wherein n cells in the memory device store n bits of data, with each cell storing one bit of data conform to the following:

Let (L1, L2, . . . , Ln) denote the levels of an x-level codeword, where 2<

=x<

=q and each level Li (for 1<

=i<

=n) is in the set {0, 1, . . . , x−

1};

let (B1, B2, . . . , Bn) denote the n bits encoded by the codeword (L1, L2, . . . , Ln), then the mapping is that for 1<

=i<

=n, Bi=Li mod 2.

46. The system as in claim 41, wherein n cells in the memory device store n bits of data, with each cell storing one bit of data conforming to the following:

Let (L1, L2, . . . , Ln) denote the levels of an x-level codeword, where 2<

=x<

=q and each level Li (for 1<

=i<

=n) is in the set {0, 1, . . . , x−

1};

let (B1, B2, . . . , Bn) denote the n bits encoded by the codeword (L1, L2, . . . , Ln), then the mapping is that for 1<

=i<

=n, Bi=(Li+1) mod 2.

47. The system as in claim 41, wherein n cells in the memory device store nk bits of data, with each cell storing k bits of data conforming to the following:

Let (L1, L2, . . . , Ln) denote the levels of an x-level codeword, where 2<

=x<

=q and each level Li (for 1<

=i<

=n) is in the set {0, 1, . . . , x−

1};

given 1<

=i<

=n, let (B1, B2, . . . , Bk) denote the k bits encoded by the ith cell of level Li, then the mapping from Li to (B1, B2, . . . , Bk) satisfies the following constraints;

for any 0<

=y<

z<

=(2̂

k)−

1, the value of (B1, B2, . . . , Bk) for Li=y is different from the value of (B1, B2, . . . , Bk) for Li=z; and

for any 0<

=z<

=q−

1, the value of (B1, B2, . . . , Bk) for Li=z is the same as the value of (B1, B2, . . . , Bk) for Li=z mod 2̂

k.

48. The system as in claim 41, wherein for n cells in the memory device, each of them stores a data symbol from the set {0, 1, . . . , Y−

1} for some integer Y, with a method of mapping that comprises;

For 1<

=i<

=n, let Lidenote the level of the ith cell, and let Si denote the data symbol stored by the ith cell, then the mapping from Li to Si satisfies the following constraints;

for any 0<

=y<

z<

=Y−

1, the value of Si for Li=y is different from the value of Si for Li=z;

for any 0<

=z<

=q−

1, the value of Si for Li=z is the same as the value of Si for Li=z mod Y.

49. The system as in claim 41, wherein for n cells in the memory device, the cells store a data symbol from the set {0, 1, . . . , (Ŷ

n)−

1} for some integer Y>

=2, with a method of mapping that comprises;

Let (L1, L2, . . . , Ln) denote the levels of the n cells, and let S denote the data symbol stored by the n cells, then the mapping from the codeword (L1, L2, . . . , Ln) to S satisfies the following constraints;

for any two different codewords, where the first codeword is an x-level codeword with x<

=Y and the second codeword is a y-level codeword with y<

=Y, the value of S for the first codeword is different from the value of S for the second codeword;

the value of S for a codeword (L1, L2, . . . , Ln) is the same as the value of S for the codeword (L1 mod Y, L2 mod Y, . . . , Ln mod Y).

50. The system as in claim 40, further comprising:

storing the configuration data set from the adaptive programming system into the memory device.

51. A memory device having:

a plurality of memory cells, each of which stores a value, where the values of the cells are mapped to discrete levels and the discrete levels represent data;

a controller that implements a coding scheme that maps codewords to data comprising a sequence of binary bits, wherein the codewords of the coding scheme are defined by a set of cell levels determined for the memory device, wherein the maximum number of cell levels for the memory device is determined based on a plurality of cell values attained by at least one cell of the memory device, in response to voltage applied by an adaptive programmer system to the cells of the memory device, such that each of the cell levels is associated with a different set of cell values of the plurality of cell values attained by the cells to which voltage is applied.

52. The memory device as in claim 51, wherein the codewords include codewords that have only level 0 and level 1, comprising 2-level codewords, or include codewords that have only level 0, level 1, and level 2 codewords, comprising 3-level codewords, and generally for a q-level codeword, include codewords that have only level 0, level 1, . . . , up to level q−

1, wherein q is an integral parameter that upper bounds the maximum number of levels that cells can possibly have.

53. The memory device as in claim 52, wherein for an x-level codeword and a y-level codeword with x<

y, if for every cell in the cell group, its level in the x-level codeword is less than or equal to its level in the y-level codeword, then the data encoded by the x-level codeword is a subset of the data encoded by the y-level codeword.

54. The memory device as in claim 53, wherein the data encoded by the x-level codeword is a prefix of the data encoded by the y-level codeword.

55. The memory device as in claim 53, wherein the q-level codewords are constant-weight codewords, namely, for x=0, 1, . . . , q−

1, all the q-level codewords have the same number of cells in level x.

56. The memory device as in claim 52, wherein n cells in the memory device store n bits of data, with each cell storing one bit of data conform to the following:

Let (L1, L2, . . . , Ln) denote the levels of an x-level codeword, where 2<

=x<

=q and each level Li (for 1<

=i<

=n) is in the set {0, 1, . . . , x−

1};

let (B1, B2, . . . , Bn) denote the n bits encoded by the codeword (L1, L2, . . . , Ln), then the mapping is that for 1<

=i<

=n, Bi=Li mod 2.

57. The memory device as in claim 52, wherein n cells in the memory device store n bits of data, with each cell storing one bit of data conforming to the following:

Let (L1, L2, . . . Ln) denote the levels of an x-level codeword, where 2<

=x<

=q and each level Li (for 1<

=i<

=n) is in the set {0, 1, . . . , x−

1};

let (B1, B2, . . . , Bn) denote the n bits encoded by the codeword (L1, L2, . . . , Ln), then the mapping is that for 1<

=i<

=n, Bi=(Li+1) mod 2.

58. The memory device as in claim 52, wherein n cells in the memory device store nk bits of data, with each cell storing k bits of data conforming to the following:

Let (L1, L2, . . . , Ln) denote the levels of an x-level codeword, where 2<

=x<

=q and each level Li (for 1<

=i<

=n) is in the set {0, 1, . . . , x−

1};

given 1<

=i<

=n, let (B1, B2, . . . , Bk) denote the k bits encoded by the ith cell of level Li, then the mapping from Li to (B1, B2, . . . , Bk) satisfies the following constraints;

for any 0<

=y<

z<

=(2̂

k)−

1, the value of (B1, B2, . . . , Bk) for Li=y is different from the value of (B1, B2, . . . , Bk) for Li=z; and

for any 0<

=z<

=q−

1, the value of (B1, B2, . . . , Bk) for Li=z is the same as the value of (B1, B2, . . . , Bk) for Li=z mod 2̂

k.

59. The memory device as in claim 52, wherein for n cells in the memory device, each of them stores a data symbol from the set {0, 1, . . . , Y−

1} for some integer Y, with a method of mapping that comprises;

For 1<

=i<

=n, let Li denote the level of the ith cell, and let Si denote the data symbol stored by the ith cell, then the mapping from Li to Si satisfies the following constraints;

for any 0<

=y<

z<

=Y−

1, the value of Si for Li=y is different from the value of Si for Li=z;

for any 0<

=z<

=q−

1, the value of Si for Li=z is the same as the value of Si for Li=z mod Y.

60. The memory device as in claim 52, wherein for n cells in the memory device, the cells store a data symbol from the set {0, 1, . . . , (Ŷ

n)−

1} for some integer Y>

=2, with a method of mapping that comprises;

Let (L1, L2, . . . , Ln) denote the levels of the n cells, and let S denote the data symbol stored by the n cells, then the mapping from the codeword (L1, L2, . . . , Ln) to S satisfies the following constraints;

for any two different codewords, where the first codeword is an x-level codeword with x<

=Y and the second codeword is a y-level codeword with y<

=Y, the value of S for the first codeword is different from the value of S for the second codeword;

the value of S for a codeword (L1, L2, . . . , Ln) is the same as the value of S for the codeword (L1 mod Y, L2 mod Y, . . . , Ln mod Y).