NONVOLATILE STORAGE USING LOW LATENCY AND HIGH LATENCY MEMORY

• US 20120096246A1
• Filed: 10/14/2010
• Published: 04/19/2012
• Est. Priority Date: 10/14/2010
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Pio, Federico
• Granted Patent: US 10,114,746 B2
• Time in Patent Office: Days
• US Class Current: 712/233
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0638 Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module address formation of the next microinstruction G06F9/26; masking faults in memories by using spares or by reconfiguring G11C29/70
• CPC Class Codes: G06F 2212/205 Hybrid memory, e.g. using both volatile and non-volatile memory
• CPC Class Codes: G06F 3/0611 in relation to response time
• CPC Class Codes: G06F 3/0638 Organizing or formatting or addressing of data
• CPC Class Codes: G06F 3/0685 Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays

Abstract

Nonvolatile storage includes first and second memory types with different read latencies. FLASH memory and phase change memory are examples. A first portion of a data block is stored in the phase change memory and a second portion of the data block is stored in the FLASH memory. The first portion of the data block is accessed prior to the second portion of the data block during a read operation.

Claims

1. An apparatus comprising:

a first memory having a first read latency; and

a second memory having a second read latency larger than the first read latency, wherein

a first portion of a data block is stored in the first memory and a second portion of the data block is stored in the second memory, the first portion of the data block being accessed prior to the second portion of the data block during a read operation.

2. The apparatus of claim 1, wherein the first memory comprises a phase change memory (PCM), and the first portion of the data block stored in the PCM is of a size that is related to a difference between latency in accessing the second memory and latency in accessing the PCM.

3. The apparatus of claim 2, wherein the second memory comprises a FLASH memory and wherein the size of the first portion of the data block stored in the PCM is determined so that accessing the first portion of the data block from the PCM occurs prior to the second portion of the data block from the FLASH memory being available for output.

4. The apparatus of claim 1, wherein at least one branch instruction is present in one of the group consisting of:

the first portion of the data block and the second portion of the data block.

5. The apparatus of claim 4, wherein the at least one branch instruction is one of the group consisting of:

a GOTO, a GOSUB, an IF-THEN, and a FOR-NEXT instruction.

6. The apparatus of claim 4, wherein the at least one branch instruction separates a first sequence of instructions from a second sequence of instructions, the second sequence of instructions having an entry point at a location within the first memory.

7. The apparatus of claim 1, additionally comprising a controller that writes frequently-updated data to the first memory.

8. A method comprising:

receiving a request to read a data block from a logical address;

reading a first portion of the data block from a phase change memory; and

reading a second portion of the data block from a FLASH memory.

9. The method of claim 8, wherein one of the first portion of the data block and the second portion of the data block includes a branch, the branch redirecting an execution of a code to a location within the phase change memory.

10. The method of claim 8, wherein a size of the first portion of the data block is related to a difference in latencies between the FLASH memory and the phase change memory.

11. The method of claim 8, wherein reading the first portion of the data block from the phase change memory occurs during a time period in between the FLASH memory receiving a read instruction and the FLASH memory transmitting the second portion of the data block.

12. The method of claim 8, further comprising generating, from the logical address, a first starting address for the first portion of the data block and a first starting address for the second portion of the data block.

13. A computer-readable medium having instructions stored thereon that when accessed result in a controller performing:

receiving a request to write a data block to a logical address;

generating at least a first starting address of a location within a phase change memory; and

generating at least a first starting address of a location within a FLASH memory.

14. The computer-readable medium of claim 13 wherein the instructions, when accessed additionally result in the controller writing the data block to the phase change memory and to the FLASH memory, the data block being written to the phase change and to the FLASH memory in an interleaving manner.

15. The computer-readable medium of claim 13 wherein the instructions, when accessed additionally result in the controller storing at least a portion of a log file in the phase change memory.

16. The computer-readable medium of claim 13 wherein the instructions, when accessed additionally result in the controller occasionally adjusting one of the group consisting of:

a first starting address of the location within the phase change memory and a first starting address of the location within the FLASH memory.

17. The computer-readable medium of claim 13 wherein the instructions, when accessed additionally result in the controller determining that the data block includes software instructions having at least one branch.

18. The computer-readable medium of claim 17, wherein the at least one branch is one of the group consisting of:

a GOTO, a GOSUB, an IF-THEN, and a FOR-NEXT instruction.

19. The computer-readable medium of claim 17 wherein the instructions, when accessed additionally result in the controller writing software instructions subsequent to the at least one branch to a location within the phase change memory.

20. The computer-readable medium of claim 19 wherein the instructions, when accessed additionally result in the controller writing additional software instructions to a second starting address within the FLASH memory subsequent to writing software instructions to the phase change memory.