INTEGRATED DATA MODEL BASED FRAMEWORK FOR DRIVING DESIGN CONVERGENCE FROM ARCHITECTURE OPTIMIZATION TO PHYSICAL DESIGN CLOSURE

• US 20120096417A1
• Filed: 10/18/2010
• Published: 04/19/2012
• Est. Priority Date: 10/18/2010
• Status: Active Grant

• Current Assignee: Algotochip Corp.
• Original Assignee: Algotochip Corp.
• Inventors: Durbha, Ananth, Ng, Pius, Padmanabhan, Satish
• Granted Patent: US 8,276,107 B2
• Time in Patent Office: Days
• US Class Current: 716/103
• CPC Class Codes: G06F 2111/04 Constraint-based CAD
• CPC Class Codes: G06F 2117/08 HW-SW co-design, e.g. HW-SW partitioning
• CPC Class Codes: G06F 30/30 Circuit design

Abstract

Systems and methods are disclosed to automatically synthesize a custom integrated circuit by receiving a specification of the custom integrated circuit including computer readable code and one or more constraints on the custom integrated circuit; encoding architecture level knowledge in a data model to generate and pass new constraints for physical synthesis of a chip specification uniquely customized to the computer readable code; receiving a look-ahead cost function during architecture optimization consistent with cost observed later in the flow after detailed physical synthesis is performed, wherein the look-ahead cost function is generated from a prior iteration and supplied to a subsequent iteration through the data model; automatically translating information available at one optimization point into a constraint for another optimization point invoked at a different place in the design flow using the data model; and synthesizing a computer readable description of the chip specification into the custom integrated circuit for semiconductor fabrication.

Claims

1. A method to automatically synthesize a custom integrated circuit, comprising:

a. receiving a specification of the custom integrated circuit including computer readable code and one or more constraints on the custom integrated circuit;

b. encoding architecture level knowledge in a data model to generate and pass new constraints for physical synthesis of a chip specification uniquely customized to the computer readable code;

c. receiving a look-ahead cost function during architecture optimization consistent with cost observed later in the flow after detailed physical synthesis is performed, wherein the look-ahead cost function is generated from a prior iteration and supplied to a subsequent iteration through the data model;

d. automatically translating information available at one optimization point into a constraint for another optimization point invoked at a different place in the design flow using the data model; and

e. synthesizing a computer readable description of the chip specification into the custom integrated circuit for semiconductor fabrication.

2. The method of claim 1, comprising creating an intra-flow inter-OE (optimization engine) sideband communication channel.

3. The method of claim 1, comprising applying pre and post fix tags to indicate if the grouping of cells in a hierarchy is a hard or soft constraint.

4. The method of claim 1, comprising storing names of with certain pre/post fix to indicate a critical path from the architecture level knowledge.

5. The method of claim 1, comprising indicating placement constraints for optimal timing with one of:

macro blocks name, hierarchy name, pragma, comment, dummy module, wrapper module.

6. The method of claim 1, comprising performing look ahead to detect true critical paths as part of cost function evaluation during optimization candidate search.

7. The method of claim 1, wherein the constraint comprises one of:

register transfer language (RTL) constraint, floor plan constraint, physical constraint, timing constraint, power constraint, system level constraint.

8. The method of claim 1, comprising providing constraint information to the data model through a netlist naming protocol.

9. The method of claim 1, comprising performing static profiling or dynamic profiling of the computer readable code.

10. The method of claim 1, whereby static profiling or dynamic profiling of the computer readable code is converted into resource constraints for cost modeling as well as physical design optimization.

11. The method of claim 1, comprising automatically generating firmware or software development kit (SDK) for the custom integrated circuit to run the computer readable code.

12. The method of claim 1, comprising selecting an architecture based on the computer readable code.

13. The method of claim 1, comprising optimizing the architecture based on static and dynamic profiling of the computer readable code.

14. The method of claim 1, comprising compiling the computer readable code into assembly code.

15. The method of claim 12, comprising linking the assembly code to generate firmware for the selected architecture.

16. The method of claim 12, comprising performing cycle accurate simulation of the firmware.

17. The method of claim 12, comprising performing dynamic profiling of the firmware.

18. The method of claim 15, comprising optimizing the architecture based on profiled firmware.

19. The method of claim 12, comprising optimizing the architecture based on the assembly code.

20. The method of claim 1, comprising generating register transfer level (RTL) code for the selected architecture and synthesizing the RTL code.