THIN FILM TRANSISTOR AND PIXEL STRUCTURE HAVING THE THIN FILM TRANSISTOR

• US 20120097955A1
• Filed: 07/12/2011
• Published: 04/26/2012
• Est. Priority Date: 10/21/2010
• Status: Active Grant

• Current Assignee: AUO Corp.
• Original Assignee: AU Optronics Corporation
• Inventors: Kao, Yih-Chyun, Huang, Chun-Yao, Wu, Chen-Yi
• Granted Patent: US 8,304,778 B2
• Time in Patent Office: Days
• US Class Current: 257/59
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A thin film transistor (TFT) and a pixel structure having the TFT are provided. The TFT is configured on a substrate. Besides, the TFT includes a gate, a gate insulation layer, a source, a channel layer, and a drain. The gate insulation layer covers the gate and the substrate. The source is configured on a portion of the gate insulation layer. The channel layer is configured on the gate insulation layer and covers a portion of the source located above the gate. The drain is configured on and electrically connected to the channel layer.

Claims

1. A thin film transistor configured on a substrate, the thin film transistor comprising:

a gate;

a gate insulation layer covering the gate and the substrate;

a source configured on a portion of the gate insulation layer;

a channel layer configured on the gate insulation layer and covering a portion of the source located above the gate; and

a drain configured on and electrically connected to the channel layer.

2. The thin film transistor as claimed in claim 1, further comprising a buffer layer between the source and the channel layer, and between the drain metal and the channel layer for lower contact resistance.

3. The thin film transistor as claimed in claim 1, further comprising a passivation layer covering the source, the channel layer, and the gate insulation layer, the passivation layer having at least one hole exposing a portion of the channel layer.

4. The thin film transistor as claimed in claim 3, wherein the drain is electrically connected to the channel layer through the at least one hole.

5. The thin film transistor as claimed in claim 3, wherein the drain further comprising an extension portion configured right above the gate and the channel layer.

6. The thin film transistor as claimed in claim 5, wherein the passivation layer is located between the extension portion and the channel layer.

7. The thin film transistor as claimed in claim 3, wherein the at least one hole is located right above the gate and the channel layer.

8. The thin film transistor as claimed in claim 1, further comprising a passivation layer covering the source, the channel layer, and the drain.

9. The thin film transistor as claimed in claim 8, wherein the channel layer further covers the gate insulation layer.

10. The thin film transistor as claimed in claim 8, wherein the drain further covers the gate insulation layer.

11. The thin film transistor as claimed in claim 1, wherein the source contacts the channel layer at a source contact region, the drain contacts the channel layer at a drain contact region, a horizontal distance from the source contact region to the drain contact region is parallel to the substrate, and the horizontal distance is greater than or equal to zero.

12. The thin film transistor as claimed in claim 1, wherein the source contacts the channel layer at a source contact region, the drain contacts the channel layer at a drain contact region, a horizontal distance from the source contact region to the drain contact region is parallel to the substrate, and the horizontal distance is smaller than 3 μ

m.

13. The thin film transistor as claimed in claim 1, wherein a material of the channel layer comprises a metal oxide semiconductor or an amorphous silicon semiconductor.

14. The thin film transistor as claimed in claim 13, wherein the metal oxide semiconductor comprises indium-gallium-zinc oxide.

15. The thin film transistor as claimed in claim 1, wherein a material of the drain comprises a transparent conductive material.

16. The thin film transistor as claimed in claim 1, wherein a material of the drain comprises metal.

17. The thin film transistor as claimed in claim 1, wherein a material of the source and a material of the drain are the same.

18. A pixel structure comprising:

the thin film transistor as claimed in claim 1; and

a pixel electrode electrically connected to the drain.

19. The pixel structure as claimed in claim 18, wherein the pixel electrode and the drain are in a same layer.

20. A circuit structure comprising the thin film transistor as claimed in claim 1.