CENTRIPETAL LAYOUT FOR LOW STRESS CHIP PACKAGE

• US 20120098120A1
• Filed: 10/21/2010
• Published: 04/26/2012
• Est. Priority Date: 10/21/2010
• Status: Abandoned Application

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yu, Chen-Hua, Tsai, Hao-Yi, Wu, Jiun Yi, Kuo, Tin-Hao
• Application Number:
  US12/908,946
• Publication Number:
  US 20120098120A1
• Time in Patent Office: Days
• US Class Current: 257/737
• CPC Class Codes: H01L 2224/02377 Fan-in arrangement
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05553 being rectangular
• CPC Class Codes: H01L 2224/05567 the external layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/13012 in top view
• CPC Class Codes: H01L 2224/13014 being circular or elliptic
• CPC Class Codes: H01L 2224/13022 the bump connector being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/1308 being stacked
• CPC Class Codes: H01L 2224/13082 Two-layer arrangements
• CPC Class Codes: H01L 2224/13109 Indium [In] as principal constituent
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13113 Bismuth [Bi] as principal constituent
• CPC Class Codes: H01L 2224/13118 Zinc [Zn] as principal constituent
• CPC Class Codes: H01L 2224/1312 Antimony [Sb] as principal constituent
• CPC Class Codes: H01L 2224/13139 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/1601 Structure
• CPC Class Codes: H01L 2224/16104 relative to the bonding area, e.g. bond pad
• CPC Class Codes: H01L 2224/16105 the bump connector connecting bonding areas being not aligned with respect to each other
• CPC Class Codes: H01L 2224/16237 the bump connector connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/1712 : Layout layout of bump connectors prior to the connecting process H01L2224/1412
• CPC Class Codes: H01L 2224/81191 : wherein the bump connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81385 : Shape, e.g. interlocking features
• CPC Class Codes: H01L 2224/81424 : Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/81447 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/17 : of a plurality of bump connectors
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01025 : Manganese [Mn]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/0103 : Zinc [Zn]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/14 : Integrated circuits

Abstract

A low-stress chip package is disclosed. The package includes two substrates. The first substrate includes an array of first conductive structures in the corner area of the chip, and an array of second conductive structures in the peripheral edge area of the chip. The first and second conductive structures each has a conductive pillar having elongated cross section in the plane parallel to the first substrate and a solder bump over the pillar. The package also includes a second substrate having an array of metal traces. The elongated pillars each form a coaxial bump-on-trace interconnect with a metal trace respectively. The long axis of the elongated cross section of a pillar in the corner area of the chip points to chip'"'"'s center area, and the long axis of the elongated cross section of a pillar in chip'"'"'s peripheral edge area aligns perpendicular to the edge.

Claims

1. A device comprising:

a chip on a first substrate;

a first conductive structure formed on the chip, the conductive structure comprising a conductive pillar and a solder bump formed over the pillar, wherein the first conductive structure has an elongated cross section in a plane parallel to the first substrate;

a metal trace formed on a second substrate facing the chip;

a solder resister layer formed over the second substrate, the solder resister layer having an opening over the metal trace; and

the first conductive structure on the chip and the metal trace in the opening of the solder resister layer formed a bump-on-trace interconnect, wherein a long axis of the elongated cross section of the conductive structure is coaxial to the trace, and the trace is aligned to point to a center portion of the chip.

2. The device of claim 1, wherein the first conductive structure is located in a peripheral portion of the chip.

3. The device of claim 2, wherein the peripheral portion of the chip includes a chip corner and a chip straight edge, wherein the bump-on-trace in the chip corner is aligned along a diagonal line of the chip and the bump-on-trace along the chip straight edge is aligned perpendicular to the chip straight edge.

4. The device of claim 1, further comprising a second conductive structure having a round cross section in the plane parallel to the first substrate.

5. The device of claim 4, wherein the second conductive structure having the round cross section is located in a central portion of the chip.

6. The device of claim 1, wherein the trace has a shape selected from a group consisting of a straight line, a bent line, and a curved line.

7. The device of claim 1, wherein the trace includes a material selected from the group consisting of copper, copper/nickel alloy, copper-IT (immersion Sn), and copper-ENEPIG (electroless nickel electroless palladium immersion gold), copper-OSP (organic solderability preservatives), aluminum, aluminum, aluminum/silicon/copper alloy, titanium, titanium nitride, tungsten, polysilicon, metal silicide, copper alloy, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, polysilicon, and combinations thereof.

8. A device comprising:

a chip on a first substrate, the chip having a central area, a corner area, and a peripheral edge area;

an array of first conductive structures having elongated cross sections formed in the corner area of the chip, the first conductive structures each comprising a conductive pillar and a solder bump formed over the pillar;

an array of second conductive structures having elongated cross sections formed in the peripheral edge area of the chip, the second conductive structures each comprising a conductive pillar and a solder bump formed over the pillar;

an array of metal traces on a second substrate facing the first substrate; and

the first and second conductive structures each forming a coaxial bump-on-trace interconnect with the metal traces respectively within ±

30 degrees,

wherein a long axis of the elongated cross sections of the first conductive structures in the corner area of the chip points to the center area of the chip, and a long axis of the elongated cross sections of the second conductive structures in the peripheral edge area of the chip aligns perpendicular to the chip'"'"'s edge.

9. The device of claim 8, further comprising an array of third conductive structures in the center area of the chip, the third conductive structures having round cross sections in the plane parallel to the first substrate.

10. The device of claim 8, wherein the first conductive structures in the corner area of the chip point to the chip center within ±

15 degrees.

11. The device of claim 8, wherein the second conductive structures in the peripheral edge area of the chip align perpendicular to the chip edge within ±

15 degrees.

12. The device of claim 8, wherein the arrays of the first and second conductive structures have predetermined layouts.

13. The device of claim 8, wherein the array of first conductive structures and the array of second conductive structures include sub-arrays.

14. The device of claim 13, wherein the sub-arrays have different predetermined layouts from each other.

15. The device of claim 8, wherein the traces have shapes selected from a group consisting of straight lines, bent lines, and curved lines.

16. The device of claim 8, wherein the bump-on-trace interconnect structures are staggered alternating structures.

17. A method of manufacturing a low stress chip package array, comprising:

a) providing a chip on a first substrate;

b) dividing the chip into a central area, a corner area, and a peripheral edge area;

c) generating a plurality of first conductive pillars in the corner area of the chip, the pillars having elongated cross sections in a plane parallel to the first substrate;

d) generating a plurality of second conductive pillars in the peripheral edge area of the chip, the pillars having elongated cross sections in a plane parallel to the first substrate;

e) forming a solder bump over each of the first and second conductive elongated pillars;

f) forming a plurality of trace lines on a second substrate;

g) coating a layer of solder resister over the second substrate;

h) forming a plurality of openings over the trace lines in the solder resister layer;

i) flipping the second substrate to face the first substrate; and

j) connecting the first and second conductive elongated pillars to the trace lines via the solder bumps,

wherein the long axes of the elongated cross sections of the first and second conductive pillars are coaxial with the corresponding trace lines, and

wherein the first conductive elongated pillars in the corner area of the chip align along a diagonal line of the chip and the second conductive elongated pillars in the peripheral edge area of the chip align perpendicular to the chip'"'"'s edge.

18. The method of manufacturing a low stress chip package as in claim 17, wherein a substantial portion of the solder resister layer is opened in the corner area and the peripheral area of the chip.

19. The method of manufacturing a low stress chip package as in claim 17, wherein a substantial portion of the solder resister is opened in the corner area, the peripheral area, and the central area of the chip.

20. The method of manufacturing a low stress chip package as in claim 17, wherein a substantial portion of the solder resister is opened in the corner area and the peripheral area, but only portions of the solder resister is opened in the central area of the chip.