METHODS AND STRUCTURE FOR ON-CHIP CLOCK JITTER TESTING AND ANALYSIS

• US 20120098571A1
• Filed: 10/26/2010
• Published: 04/26/2012
• Est. Priority Date: 10/26/2010
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: LSI Corporation (Broadcom, Inc.)
• Inventors: Feist, Douglas J., Feist, Tracy J.
• Granted Patent: US 8,619,935 B2
• Time in Patent Office: Days
• US Class Current: 327/10
• CPC Class Codes: G01R 29/027 Indicating that a pulse characteristic is either above or below a predetermined value or within or beyond a predetermined range of values
• CPC Class Codes: G01R 31/31708 Analysis of signal quality G01R31/31901 takes precedence; measuring frequencies or analysing frequency spectra per se G01R23/00; measuring non-linear distortion per se G01R23/20
• CPC Class Codes: G01R 31/31709 Jitter measurements; Jitter generators measuring jitter, noise figure or signal-to-noise ratio per se G01R29/26; analysis of tester signals G01R31/31901
• CPC Class Codes: G01R 31/31727 Clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing clocks G01R31/31725 takes precedence; concerning scan test G01R31/318552, for tester hardware G01R31/31922

Abstract

Methods and structure for on-chip self-test of clock jitter for an application clock signal generated within an integrated circuit (IC). Features and aspects hereof provide for acquisition of samples of an application clock signal within the IC and counting the number of samples having a predetermined value. The count is compared to acceptable limits range values to generate a pass/fail signal of the IC use by external automated. A sample clock is generated based on the reference clock used by a Phase Locked Loop (PLL) circuit. An incremental delay is added to the sample clock pulse such that the sequence of samples “walk” through an application clock pulse waveform to sense clock jitter at various points of the waveform based on the counts. Acceptable limits range for the count at each sampled point, the incremental delay, and the number of samples at each delayed value may be user programmed.

Claims

1. An integrated circuit (IC) comprising:

a Phase Locked Loop circuit (PLL) having an input coupled to receive a reference clock signal and adapted to generate and output an application clock signal;

a sampling control circuit having an input coupled to receive the reference clock signal and having an input coupled to receive the application clock signal, the sampling control circuit adapted to acquire a plurality of samples of the application clock signal at each of a plurality of sample points, wherein the plurality of sample points span a period of time that comprises multiple clock periods of the application clock signal, wherein the plurality of samples are acquired based on the reference clock signal, wherein the plurality of sample points are offset in time relative to one another to sample different points of the multiple clock periods of the application clock signal, and wherein the sampling control circuit is further adapted to generate and output a count of the number of samples of the plurality of samples having a predetermined value at each of the plurality of sample points; and

an analysis circuit having an input coupled to receive the count, the analysis circuit adapted to determine whether the count is within acceptable limits and further adapted to generate a pass/fail output signal indicating whether the count is within the acceptable limits.

2. The IC of claim 1

wherein the sampling control circuit further comprises:

a programmable delay line circuit having an input coupled to receive the reference clock signal and adapted to generate a sample clock signal,

wherein the sampling control circuit uses the sample clock signal to acquire each of the plurality of samples and wherein the sample clock signal is delayed a predetermined amount for each sequential sample point of the plurality of sample points.

3. The IC of claim 2

wherein the sampling control circuit further comprises:

an edge detection circuit having an input coupled to receive the application clock signal and having an input coupled to receive the sample clock signal, the edge detection circuit adapted to latch the present value of the application clock signal in response to sensing an edge on the sample clock signal and is further adapted to apply the latched value of the application clock signal to an output of the edge detection circuit.

4. The IC of claim 3

wherein the edge detection circuit further comprises an edge-triggered flip-flop having an input coupled to receive the sample clock signal and having an input coupled to receive the application clock signal and adapted to latch the value of the application clock signal responsive to each rising edge of each pulse of the sample clock signal.

5. The IC of claim 3

wherein the sampling control circuit further comprises:

a counter circuit having an input coupled to receive the latched present value of the application clock circuit and having an input coupled to receive the sample clock signal, wherein the counter circuit is adapted to increment a counter for each latched value having the predetermined value in response to the rising edge of each pulse of the sample clock pulse, and wherein the counter circuit is further adapted to output the count from the counter circuit.

6. The IC of claim 1

wherein the analysis circuit further comprises a acceptable limit comparator circuit having an input coupled to receive the count and having an input coupled to receive a predetermined acceptable limits range, the comparator circuit adapted to compare the count with the acceptable limits range and further adapted to generate a pass/fail output signal indicating whether the count is within the acceptable limits range.

7. The IC of claim 6 further comprising:

a limits range memory adapted to store a plurality of acceptable limits ranges each range associated with a corresponding sample point of the plurality of sample points and further adapted to apply the acceptable limits range corresponding to a present sample point of the plurality of sample points to the comparator circuit, wherein the limits range memory is further adapted to receive the acceptable limits ranges from an external source.

8. The IC of claim 7 further comprising:

a count data memory adapted to store the count corresponding to each sample point of the plurality of sample points and further adapted to apply the count corresponding to the present sample point to the comparator circuit.

9. A method operable within an integrated circuit (IC) for testing and analyzing jitter of a Phase Locked Loop (PLL) generated application clock signal within the IC, the method comprising:

generating a sample clock signal based on a reference clock signal used by the PLL;

acquiring a plurality of samples of the application clock signal at each of a plurality of sample points, wherein the plurality of sample points span a period of time that comprises multiple clock periods of the application clock signal, wherein the plurality of samples are acquired based on the reference clock signal, wherein plurality of sample points are offset in time relative to one another to sample different points of the multiple clock periods of the application clock signal,

generating a count of the number of samples having a predetermined value;

determining whether the count is within acceptable limits; and

generating a pass/fail output signal indicating whether the count is within the acceptable limits.

10. The method of claim 9

wherein the step of acquiring further comprises:

programming a programmable delay line circuit in the IC to generate a sample clock signal delayed from the reference clock signal wherein the sample clock signal is delayed a predetermined amount for each sequential sample point of the plurality of sample points; and

acquiring each of the plurality of samples based on the sample clock signal.

11. The method of claim 10

wherein the step of generating the count further comprises:

applying the application clock signal and the sample clock signal to an edge detection circuit of the IC to latch the present value of the application clock signal in response to sensing an edge on the sample clock signal; and

applying the latched present value in the edge detection circuit and the sample clock signal to a counter circuit to count the number of latched present values of the application clock signal having the predetermined value.

12. The method of claim 10

wherein the step of generating the count further comprises:

applying the application clock signal and the sample clock signal to an edge-triggered flip-flop of the IC to latch the present value of the application clock signal in response to sensing an edge on the sample clock signal; and

applying the latched present value in the edge-triggered flip-flop circuit and the sample clock signal to a counter circuit to count the number of latched present values of the application clock signal having the predetermined value.

13. The method of claim 9

wherein the step of determining further comprises:

comparing the count to an acceptable limits range; and

generating the pass/fail output signal indicating whether the count is within the acceptable limits range.

14. The method of claim 13 further comprising:

receiving the acceptable limits range from an external source; and

storing the acceptable limits range in a memory within the IC.

15. A circuit within an integrated circuit (IC) for testing jitter of an application clock signal generated within the IC, the circuit comprising:

a sample clock generator coupled to receive an external reference clock signal and adapted to generate a sample clock signal based on the reference clock signal wherein the reference clock signal is used within the IC to generate the application clock signal and wherein the sample clock signal is generated by adding an incremental delay duration to each of a plurality of pulses of the reference clock signal received by the sample clock generator;

an edge-triggered flip-flop coupled to receive the application clock signal and coupled to receive the sample clock signal wherein the flip-flop is adapted to latch the present value of the application clock signal responsive to each rising edge of the sample clock signal and is further adapted to output the present latched value;

a counter coupled to receive the sample clock signal and coupled to receive the present latched value wherein the counter is adapted to increment a count value responsive detecting a logic high on the present latched value at a rising edge of the sample clock signal and is adapted to output its present count value; and

a comparator coupled to receive the present count value and coupled to receive the sample clock signal wherein the comparator is adapted to compare the present count value to an acceptable limits range at a rising edge of the sample clock signal and is adapted to output a pass/fail signal indicating whether the present count value is within the acceptable limits range or is outside the acceptable limits range.

16. The circuit of claim 15 further comprising:

a limits range memory adapted to store a plurality of acceptable limits ranges, each range associated with a corresponding latched present value, the limits range memory further adapted to apply the acceptable limits range corresponding to a present latched value to the comparator circuit, wherein the limits range memory is further adapted to receive the acceptable limits ranges from an external source.

17. The circuit of claim 16 further comprising:

a count data memory adapted to store the present count value corresponding to each present latched value and further adapted to apply the present count value corresponding to the present latched value to the comparator circuit.

18. The circuit of claim 15

wherein the sample clock generator further comprises:

a programmable delay line coupled to receive the reference clock signal and adapted add a presently programmed delay to the reference clock signal to generate the sample clock signal; and

control logic coupled to receive the reference clock signal and coupled with the programmable delay line wherein the control logic is adapted to re-program the presently programmed delay in response to each of a plurality of rising edges of the reference clock signal wherein each re-programming of the programmable delay line adds an incremental delay amount to the programmable delay line.