INTEGRATED ACOUSTIC BANDGAP DEVICES FOR ENERGY CONFINEMENT AND METHODS OF FABRICATING SAME

• US 20120098611A1
• Filed: 12/29/2011
• Published: 04/26/2012
• Est. Priority Date: 12/17/2007
• Status: Active Grant

• Current Assignee: Cymatics Laboratories Corp.
• Original Assignee: Cymatics Laboratories Corp.
• Inventors: Sinha, Rajarishi, Gammel, Peter Ledel, Mastrapasqua, Marco, Safar, Hugo
• Granted Patent: US 8,564,174 B2
• Time in Patent Office: Days
• US Class Current: 331/158
• CPC Class Codes: H01L 27/02 including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
• CPC Class Codes: H03H 9/0557 the other elements being buried in the substrate
• CPC Class Codes: H03H 9/175 Acoustic mirrors
• CPC Class Codes: H03H 9/564 implemented with thin-film techniques
• CPC Class Codes: H03H 9/589 Acoustic mirrors
• CPC Class Codes: Y10T 29/42 Piezoelectric device making

Abstract

The present invention is directed to monolithic integrated circuits incorporating an oscillator element that is particularly suited for use in timing applications. The oscillator element includes a resonator element having a piezoelectric material disposed between a pair of electrodes. The oscillator element also includes an acoustic confinement structure that may be disposed on either side of the resonator element. The acoustic confinement element includes alternating sets of low and high acoustic impedance materials. A temperature compensation layer may be disposed between the piezoelectric material and at least one of the electrodes. The oscillator element is monolithically integrated with an integrated circuit element through an interconnection. The oscillator element and the integrated circuit element may be fabricated sequentially or concurrently.

Claims

1. A method of fabricating an integrated circuit comprising:

forming an integrated circuit device layer on a semiconductor substrate, the integrated circuit device layer having a plurality of individual devices formed therein;

forming an interconnect layer over the interconnect device layer, the metal interconnect layer having at least one metal layer therein;

forming an insulating over said interconnect layer;

forming a first layer selected from one of a low acoustic impedance material and a high acoustic impedance material on the dielectric layer;

forming a second layer selected from the other of a high acoustic impedance material and a low acoustic impedance material on the first layer, the first and second layers together forming a first period consisting of one layer of high acoustic impedance and one layer of low acoustic impedance;

forming a bottom electrode layer over the second layer;

forming a piezoelectric layer over the bottom electrode layer;

forming a top electrode layer on the piezoelectric layer;

forming a third layer selected from one of a low acoustic impedance material and a high acoustic impedance material on the top electrode layer;

forming a fourth layer selected from the other of a high acoustic impedance material and a low acoustic impedance material on the first layer, the third and fourth layers together forming a second period consisting of one layer of high acoustic impedance and one layer of low acoustic impedance, wherein the piezoelectric material is substantially encapsulated by the bottom and top electrodes and first and second periods.

2. The method of claim 1 further comprising electrically interconnecting one of the top electrodes and bottom electrodes with a selected one of the at least one metal layers in the metal interconnect layers.

3. The method of claim 2 wherein the bottom electrode is interconnected with the at least one metal layer by forming a via from the bottom electrode and through the first period and the dielectric layer over the metal interconnect layer, stopping the via at the selected one of the at least one metal layers in the metal interconnect layer and filling the via with metal to form the electrical interconnection.

4. The method of claim 2 wherein the top electrode is interconnected with the at least one metal layer by forming a trace from the top electrode to the selected one of the at least one metal layers in the metal interconnect layers.

5. The method of claim 4 wherein the trace is formed through a dielectric region adjacent the piezoelectric material, top and bottom electrodes and first and second periods.

6. The method of claim 5 further comprising forming one or more vias in the dielectric region and filling those vias with metal to electrically interconnect the top electrode with the selected one of the at least one metal layers in the metal interconnect layers.

7. The method of claim 6 further comprising forming a temperature compensation layer on the piezoelectric layer and forming the top electrode on the temperature compensation layer.

8. The method of claim 1 further comprising patterning the bottom electrode layer to form at least two electrodes, the first electrode being an oscillator element bottom electrode and the second electrode being a filter element lower electrode.

9. The method of claim 8 further comprising patterning the piezoelectric layer to form at least two piezoelectric regions, the first piezoelectric region in contact with the oscillator element bottom electrode and the second piezoelectric region being in contact with the filter element lower electrode.

10. A method of fabricating an integrated circuit comprising:

forming an active device layer having a plurality of semiconductor devices on a semiconductor substrate;

forming an interconnect structure integrated with the active device layer the interconnect structure having at least one metal layer;

forming a circuit element comprising a resonator element embedded in an acoustic confinement structure on the semiconductor substrate; and

monolithically integrating the oscillator element with the interconnect structure.

11. The method of claim 10 wherein the monolithic integration further comprises:

forming a metal trace between an electrode of the resonator element to a selected one of the metal layers in the interconnect structure.

12. The method of claim 11 wherein the acoustic confinement structure is formed by:

depositing a first multilayer period structure adjacent the interconnect structure, wherein the multilayer period has one layer of low acoustic impedance and one layer of high acoustic impedance;

forming the resonant element comprising a first electrode layer, a piezoelectric layer and a second electrode over the first multilayer period structure; and

forming a second multilayer period structure over the resonant element thereby embedding the resonant element in the first and second multilayer period structure.

13. The method of claim 12 further comprising forming a temperature compensation layer on the piezoelectric layer and forming the second periodic structure over the temperature compensation layer.

14. An integrated circuit device comprising:

a circuit element means having a resonator means and an acoustic confinement means for preventing the ultrasonic wave from propagating away from the resonator means; and

an integrated circuit means comprising a plurality of semiconductor device elements and an interconnect means;

wherein the circuit element means is monolithically connected to the integrated circuit means in a unitary structure.

15. The integrated circuit of claim 14 wherein the resonator means has first and second electrodes and wherein one of the first and second electrodes is electrically connected to the integrated circuit interconnect means.

16. The integrated circuit device of claim 14 wherein the circuit element means further comprises a temperature compensation means.

17. The integrated circuit of claim 14 wherein the acoustic confinement means provides the circuit element means with a bandgap at a predetermined frequency f₀.

18. The integrated circuit of claim 17 wherein, in operation, the resonator means vibrates within the acoustic confinement means.

19. The integrated circuit of claim 14 wherein the oscillator means is an acoustic band gap structure.

20. The integrated circuit of claim 17 wherein the acoustic confinement means has a peak reflectivity at the predetermined frequency f₀.

21. The integrated circuit of claim 14 wherein the acoustic confinement means is a package for the resonator means.

22. The integrated circuit of claim 14 wherein the circuit element means is an oscillator means.

23. The integrated circuit of claim 14 wherein the circuit element means is a filter means.

24. The integrated circuit of claim 22 wherein the circuit element means is an oscillator means and a filter means.