NONVOLATILE SEMICONDUCTOR MEMORY DEVICE

• US 20120099374A1
• Filed: 10/20/2011
• Published: 04/26/2012
• Est. Priority Date: 10/21/2010
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: MATSUNAGA, Yasuhiko
• Granted Patent: US 8,498,155 B2
• Time in Patent Office: Days
• US Class Current: 365/185.05
• CPC Class Codes: H01L 23/485 consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/41 of a memory region comprising a cell select transistor, e.g. NAND

Abstract

A nonvolatile semiconductor memory device includes a substrate including device regions extending in a first direction, a memory cell array region including a plurality of memory cells disposed on the device regions, bit lines extending in the first direction, a sense amplifier circuit connected to ends of the bit lines, and bit line contacts connecting device regions to bit lines. The memory cell array region includes first to N-th regions where N is an integer of two or more, and a K-th region is located at a greater distance from the sense amplifier circuit than a (K−1)-th region, where K is an arbitrary integer of 2 to N. Contact resistance of the bit line contacts in the K-th region is lower than contact resistance of the bit line contacts in the (K−1)-th region, each device region having constant width in the memory cell array region.

Claims

1. A nonvolatile semiconductor memory device comprising:

a substrate;

device regions formed in the substrate to extend in a first direction which is parallel to a surface of the substrate;

a memory cell array region including a plurality of memory cells disposed on the device regions;

bit lines disposed above the substrate to extend in the first direction;

a sense amplifier circuit electrically connected to the bit lines at ends of the bit lines on one side; and

bit line contacts disposed on the device regions to electrically connect the device regions to the bit lines,

wherein

the memory cell array region includes first to N-th regions where N is an integer of two or more,

a K-th region is located at a greater distance from the sense amplifier circuit than a (K−

1)-th region, where K is an arbitrary integer of 2 to N,

contact resistance of the bit line contacts in the K-th region is lower than contact resistance of the bit line contacts in the (K−

1)-th region, and

a width of each device region is constant in the memory cell array region.

2. The device of claim 1, wherein

an impurity concentration of diffusion layers disposed under the bit line contacts in the K-th region is greater than an impurity concentration of diffusion layers disposed under the bit line contacts in the (K−

1)-th region.

3. The device of claim 2, wherein

the impurity concentrations of the diffusion layers disposed under the bit line contacts in the first to N-th regions are 1×

10²⁰ cm<sup>−

3</sup> to 1×

10²² cm<sup>−

3</sup>.

4. The device of claim 1, wherein

a distance between the surface of the substrate and a bottom of the bit line contacts in the K-th region is greater than a distance between the surface of the substrate and a bottom of the bit line contacts in the (K−

1)-th region.

5. The device of claim 4, wherein

the distances between the surface of the substrate and bottoms of the bit line contacts in the first to N-th regions are 100 nm or less.

6. The device of claim 1, wherein

in a plane parallel to the surface of the substrate, a sectional area of each bit line contact in the K-th region is greater than a sectional area of each bit line contact in the (K−

1)-th region.

7. The device of claim 1, wherein

the contact resistance of each bit line contact is 100 kΩ

to 10 MΩ

.

8. The device of claim 1, wherein

the first to N-th regions have stripe shapes extending in a second direction which is perpendicular to the first direction.

9. the device of claim 1, wherein

the sense amplifier circuit comprises a plurality of sense amplifiers, each of which is electrically connected to a bit line.

10. A nonvolatile semiconductor memory device comprising:

a substrate;

device regions formed in the substrate to extend in a first direction which is parallel to a surface of the substrate;

a memory cell array region including a plurality of memory cells disposed on the device regions;

first bit lines disposed above the substrate to extend in the first direction, and electrically connected to a first sense amplifier circuit on the substrate at ends of the first bit lines on one side;

second bit lines disposed above the substrate to extend in the first direction, and electrically connected to a second sense amplifier circuit on the substrate at ends of the second bit lines on the other side;

first bit line contacts disposed on the device regions to electrically connect the device regions to the first bit lines; and

second bit line contacts disposed on the device regions to electrically connect the device regions to the second bit lines,

wherein

the memory cell array region includes first to N-th regions where N is an integer of two or more,

a K-th region is located at a greater distance from the first sense amplifier circuit than a (K−

1)-th region, where K is an arbitrary integer of 2 to N,

contact resistance of the first bit line contacts in the K-th region is lower than contact resistance of the first bit line contacts in the (K−

1)-th region,

the K-th region is located at a smaller distance from the second sense amplifier circuit than the (K−

1)-th region,

contact resistance of the second bit line contacts in the K-th region is higher than contact resistance of the second bit line contacts in the (K−

1)-th region, and

a width of each device region is constant in the memory cell array region.

11. The device of claim 10, wherein

an impurity concentration of diffusion layers disposed under the first bit line contacts in the K-th region is greater than an impurity concentration of diffusion layers disposed under the first bit line contacts in the (K−

1)-th region, and

an impurity concentration of diffusion layers disposed under the second bit line contacts in the K-th region is smaller than an impurity concentration of diffusion layers disposed under the second bit line contacts in the (K−

1)-th region.

12. The device of claim 11, wherein

the impurity concentrations of the diffusion layers disposed under the first and second bit line contacts in the first to N-th regions are 1×

10²⁰ cm<sup>−

3</sup> to 1×

10²² cm<sup>−

3</sup>.

13. The device of claim 10, wherein

a distance between the surface of the substrate and a bottom of the first bit line contacts in the K-th region is greater than a distance between the surface of the substrate and a bottom of the first bit line contacts in the (K−

1)-th region, and

a distance between the surface of the substrate and a bottom of the second bit line contacts in the K-th region is smaller than a distance between the surface of the substrate and a bottom of the second bit line contacts in the (K−

1)-th region.

14. The device of claim 13, wherein

the distances between the surface of the substrate and bottoms of the first and second bit line contacts in the first to N-th regions are 100 nm or less.

15. The device of claim 10, wherein

in a plane parallel to the surface of the substrate, a sectional area of each first bit line contact in the K-th region is greater than a sectional area of each first bit line contact in the (K−

1)-th region, and

in the plane parallel to the surface of the substrate, a sectional area of each second bit line contact in the K-th region is smaller than a sectional area of each second bit line contact in the (K−

1)-th region.

16. The device of claim 10, wherein

the first and second bit lines are alternately disposed along a second direction which is perpendicular to the first direction.

17. The device of claim 10, wherein

the contact resistance of each of the first and second bit line contacts is 100 kΩ

to 10 MΩ

.

18. The device of claim 10, wherein

the first to N-th regions have stripe shapes extending in a second direction which is perpendicular to the first direction.

19. The device of claim 10, wherein

the first sense amplifier circuit comprises a plurality of first sense amplifiers, each of which is electrically connected to a first bit line, and

the second sense amplifier circuit comprises a plurality of second sense amplifiers, each of which is electrically connected to a second bit line.