NONVOLATILE MEMORY DEVICE AND METHOD OF READING THE SAME USING DIFFERENT PRECHARGE VOLTAGES

• US 20120099387A1
• Filed: 10/25/2011
• Published: 04/26/2012
• Est. Priority Date: 10/25/2010
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Shim, Sunil, Lee, Woonkyung, Jang, Jaehoon, Kim, Kihyun
• Granted Patent: US 8,488,402 B2
• Time in Patent Office: Days
• US Class Current: 365/189.05
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 2216/14 Circuits or methods to write a page or sector of information simultaneously into a nonvolatile memory, typically a complete row or word line in flash memory
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 29/7926 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels

Abstract

A nonvolatile memory device includes a substrate, multiple doping regions, multiple cell strings and multiple page buffers. The doping regions extend in a first direction along the substrate and are spaced apart from one another in a second direction. The cell strings are provided according to a specific pattern between adjacent first and second doping regions among the multiple regions, each of the cell strings including multiple cell transistors stacked in a third direction perpendicular to the substrate. The page buffers are connected to the cell strings through bit lines, the page buffers being configured to provide precharge voltages to the bit lines during a read operation. Levels of the precharge voltages provided to the bit lines vary depending on distances between the cell strings and at least one of the first and second doping regions, respectively.

Claims

1. A nonvolatile memory device comprising:

a substrate;

a plurality of doping regions extending in a first direction along the substrate and being spaced apart from one another in a second direction;

a plurality of cell strings provided according to a specific pattern between adjacent first and second doping regions among the plurality of doping regions, each of the cell strings comprising a plurality of cell transistors stacked in a third direction perpendicular to the substrate; and

a plurality of page buffers connected to the plurality of cell strings through a plurality of bit lines, the page buffers being configured to provide precharge voltages to the bit lines during a read operation,

wherein levels of the precharge voltages provided to the bit lines vary depending on distances between the cell strings and at least one of the first and second doping regions, respectively.

2. The nonvolatile memory device of claim 1, wherein the levels of the precharge voltages provided to the bit lines are controlled differently depending on the distances between the cell strings and a closest doping region of the first and second doping regions, respectively.

3. The nonvolatile memory device of claim 2, wherein as the distance between each of the cell strings and the respective closest doping region increases, the levels of the precharge voltages are reduced.

4. The nonvolatile memory device of claim 2, wherein as the distance between each of the cell strings and the closest respective doping region increases, the levels of the precharge voltages are increased.

5. The nonvolatile memory device of claim 1, further comprising:

control logic configured to generate at least one load signal to be provided to the page buffers,

wherein each of the pager buffers comprises a latch circuit and a load transistor, the load transistor electrically connecting a power supply node to one bit line among the plurality of bit lines through the latch circuit in response to at least one load signal.

6. The nonvolatile memory device of claim 5, wherein the load transistor of each of the page buffers has a threshold voltage controlled the distance between each of the cell strings and the closest respective doping region.

7. The nonvolatile memory device of claim 5, wherein the control logic is configured to change a level of at least one load signal provided to the page buffers depending on the distances between the cell strings and the first and second doping regions, respectively.

8. The nonvolatile memory device of claim 7, wherein the page buffers are divided into m groups, where m is an integer greater than or equal to 1, depending on the distances between the cell strings and the first and second doping regions, respectively, and wherein the control logic is configured to provide load signals having different levels to the m groups of the page buffers respectively.

9. The nonvolatile memory device of claim 1, further comprising:

control logic configured to generate at least one load signal and one select signal provided to the plurality of page buffers,

wherein each of the page buffers comprises;

a sharing circuit configured to be connected to adjacent two bit lines among the bit lines and to select one of the adjacent bit lines in response to the select signal;

a latch circuit connected to the sharing circuit; and

a load transistor connected between the power supply node and the latch circuit, electrically connecting the power supply node to the selected bit line between the adjacent bit lines through the latch circuit and the sharing circuit under control of at least one load signal.

10. The nonvolatile memory device of claim 9, wherein the control logic is further configured to change a level of at least one load signal being provided to the page buffers depending on distances between the plurality of cell strings and the first and second doping regions, respectively.

11. The nonvolatile memory device of claim 10, wherein the plurality of bit lines is divided into m groups, where m is an integer greater than or equal to 1, depending on the distances between the plurality of cell strings and the first and second doping regions, respectively, and wherein the control logic is further configured to provide m load signals to the page buffers, the m load signals having different levels and correspond to the m groups of the bit lines respectively.

12. The nonvolatile memory device of claim of claim 11, wherein each of the page buffers is configured to receive two load signals having different levels corresponding to the adjacent bit lines among m load signals having different levels, respectively.

13. The nonvolatile memory device of claim 12, wherein in each of the page buffers, one of the two load signals having different levels is provided to the load transistor in response to the select signal.

14. The nonvolatile memory device of claim 10, wherein the plurality of page buffers is divided into n groups, where n is an integer greater than or equal to 1, depending on distance between the plurality of cell strings and the first and second doping regions, respectively, and wherein the control logic is further configured to provide n drive signals to the n groups of the page buffers respectively.

15. The nonvolatile memory device of claim 14, wherein the control logic is further configured to change a level of each of the n drive signals according to the select signal.

16. The nonvolatile memory device of claim 1, wherein the read operation comprises a verification reading operation.

17. A method of reading a memory cells in a plurality of cell strings of a nonvolatile memory device, the method comprising:

setting a precharge voltage for each cell string of the plurality of cell strings, a level of the precharge voltage comprising one of a plurality of different precharge voltage levels depending on a distance of the cell string from a doping region on a substrate; and

providing the set precharge voltage to each cell string of the plurality of cell strings through a plurality of bit lines connected to the plurality of cell strings.

18. The method of claim 17, wherein a first precharge voltage is set for each cell string a first distance from the doping region and a second precharge voltage is set for each cell string a second distance from the doping region, wherein the first distance is less than the second distance and the first precharge voltage is greater than the second precharge voltage.

19. The method of claim 18, wherein a third precharge voltage is set for each cell string a third distance from the doping region, wherein the second distance is less than the third second distance and the second precharge voltage is greater than the third precharge voltage.

20. The method of claim 17, wherein the precharge voltages are provided to the plurality of cell strings lines by a corresponding plurality of page buffers connected to the plurality of cell strings through the plurality of bit lines.