SYSTEM FOR CONTROLLING AN IN-VEHICLE DEVICE

• US 20120101656A1
• Filed: 08/30/2011
• Published: 04/26/2012
• Est. Priority Date: 10/21/2010
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Nito, Yoshiharu, Suzuki, Tsuneo
• Granted Patent: US 8,825,220 B2
• Time in Patent Office: Days
• US Class Current: 701/1
• CPC Class Codes: B60R 25/20 Means to switch the anti-theft system on or off

Abstract

According to one embodiment, a system for controlling an in-vehicle device is provided. The system has an in-vehicle device and an electronic control unit. The electronic control unit generates control signals to control the in-vehicle device and transmits the generated control signals to the in-vehicle device. The in-vehicle device has a semiconductor integrated circuit and a semiconductor memory circuit. The semiconductor integrated circuit is capable of performing a plurality of functional operations. The semiconductor memory circuit stores pieces of setting information necessary to perform the respective functional operations. The electronic control unit has a designation signal generation unit to output designation signals as the control signals. Each of the designation signals designates one of the pieces of setting information to be read from the semiconductor memory circuit. The semiconductor integrated circuit receives the designated one of the pieces of setting information which is read from the semiconductor memory circuit.

Claims

1. A system for controlling an in-vehicle device, comprising an in-vehicle device and an electronic control unit, the electronic control unit generating control signals to control the in-vehicle device and transmitting the generated control signals to the in-vehicle device via a wire harness, wherein

the in-vehicle device is provided with a semiconductor integrated circuit and a semiconductor memory circuit, the semiconductor integrated circuit being capable of performing a plurality of functional operations, the semiconductor memory circuit storing pieces of setting information which are necessary to perform the respective functional operations,

the electronic control unit is provided with a designation signal generation unit to output designation signals as the control signals, each of the designation signals designating one of the pieces of setting information to be read from the semiconductor memory circuit, and

the semiconductor integrated circuit receives the designated one of the pieces of setting information which is read from the semiconductor memory circuit according to each of the outputted designation signals.

2. The system according to claim 1, wherein the electronic control unit is provided with an encoder to encode and transmit the designation signals and the semiconductor integrated circuit includes a decoder which decodes the received encoded designation signals to designate the pieces of setting information stored in the semiconductor memory circuit respectively.

3. The system according to claim 1, wherein the pieces of setting information are stored in the semiconductor memory circuit, in a channel unit, respectively.

4. The system according to claim 3, wherein the electronic control unit designates one of the channels to be read, by the designation signals.

5. The system according to claim 3, wherein

the semiconductor integrated circuit is provided with a memory read control unit and a majority determination calculating unit,

the semiconductor memory circuit stores plural sets of n-multiplexed information pieces which are obtained by multiplexing the respective pieces of setting information of the channel unit, where “

n”

is an odd number equal to or greater than three,

the memory read control unit controls the semiconductor memory circuit so as to read one of the sets of the n-multiplexed information pieces designated by one of the designation signals, and

the majority determination calculating unit receives the read one of the sets of the n-multiplexed information pieces and determines one of the n-multiplexed information pieces to be used in the semiconductor integrated circuit, by majority determination logic.

6. The system according to claim 1, wherein the semiconductor integrated circuit is provided with a circuit to generate a trigger signal to start reading one of the pieces of setting information from the semiconductor memory circuit, the trigger signal being generated when power is applied to the semiconductor integrated circuit, which results in that the semiconductor integrated circuit outputs a read start signal and address signals to the semiconductor memory circuit automatically.

7. The system according to claim 1, wherein the semiconductor integrated circuit is provided with a memory read control unit, the memory read control unit receiving the designation signals and the trigger signal from the electronic control unit and outputting a read start signal and address signals to the semiconductor memory circuit.

8. The system according to claim 2, wherein the pieces of setting information are stored in the semiconductor memory circuit, in a channel unit, respectively.

9. The system according to claim 4, wherein

the semiconductor integrated circuit is provided with a memory read control unit and a majority determination calculating unit,

the semiconductor memory circuit stores plural sets of n-multiplexed information pieces which are obtained by multiplexing the respective pieces of setting information of the channel unit, where “

n”

is an odd number equal to or greater than three

the memory read control unit controls the semiconductor memory circuit so as to read one of the sets of the n-multiplexed information pieces designated by one of the designation signals, and

the majority determination calculating unit receives the read one of the sets of the n-multiplexed information pieces and determines one of the n-multiplexed information pieces to be used in the semiconductor integrated circuit, by majority determination logic.

10. The system according to claim 2, wherein the semiconductor integrated circuit is provided with a circuit to generate a trigger signal to start reading one of the pieces of setting information from the semiconductor memory circuit, the trigger signal being generated when power is applied to the semiconductor integrated circuit, which results in that the semiconductor integrated circuit outputs a read start signal and address signals to the semiconductor memory circuit automatically.

11. The system according to claim 3, wherein the semiconductor integrated circuit is provided with a circuit to generate a trigger signal to start reading one of the pieces of setting information from the semiconductor memory circuit, the trigger signal being generated when power is applied to the semiconductor integrated circuit, which results in that the semiconductor integrated circuit outputs a read start signal and address signals to the semiconductor memory circuit automatically.

12. The system according to claim 4, wherein the semiconductor integrated circuit is provided with a circuit to generate a trigger signal to start reading one of the pieces of setting information from the semiconductor memory circuit, the trigger signal being generated when power is applied to the semiconductor integrated circuit, which results in that the semiconductor integrated circuit outputs a read start signal and address signals to the semiconductor memory circuit automatically.

13. The system according to claim 5, wherein the semiconductor integrated circuit is provided with a circuit to generate a trigger signal to start reading one of the pieces of setting information from the semiconductor memory circuit, the trigger signal being generated when power is applied to the semiconductor integrated circuit, which results in that the semiconductor integrated circuit outputs a read start signal and address signals to the semiconductor memory circuit automatically.

14. The system according to claim 1, wherein the designation signals are static.

15. The system according to claim 2, wherein the designation signals are static.