MEMORY AGENT TO ACCESS MEMORY BLADE AS PART OF THE CACHE COHERENCY DOMAIN

• US 20120102273A1
• Filed: 06/29/2009
• Published: 04/26/2012
• Est. Priority Date: 06/29/2009
• Status: Abandoned Application

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Chang, Jichuan, Partha, Paranathan, Lim, Kevin
• Application Number:
  US13/380,490
• Publication Number:
  US 20120102273A1
• Time in Patent Office: Days
• US Class Current: 711/143
• CPC Class Codes: G06F 12/0692 Multiconfiguration, e.g. local and global addressing
• CPC Class Codes: G06F 12/0815 Cache consistency protocols

Abstract

A system and method is shown wherein a memory agent module to identify a memory command related to virtual memory pages associated with a memory blade and maintain and optimize cache coherency for such pages. The system and method also includes a memory module, operatively connected to the memory agent that includes a page cache used by the memory agent to manage the virtual memory page. Further, the system and method includes a transmission module to transmit the memory command to the memory blade, as well as data structures to facilitate the page migration between the compute blade'"'"'s local memory and remote memory on the memory blade.

Claims

1. A computer system comprising:

a memory agent module to identify a memory command related to a virtual memory page associated with a memory blade;

a memory module, operatively connected to the memory agent, that includes a page cache used by the memory agent to manage the virtual memory page; and

a transmission module to transmit the memory command to the memory blade.

2. The computer system of claim 1, wherein the memory agent includes at least one of the memory agent on a motherboard of the computer system, the memory agent as part of a socket on the computer system, or the memory agent as part of a memory controller on the computer system.

3. The computer system of claim 1, wherein the memory agent includes a cache coherence protocol engine to filter out unnecessary access to the memory blade, and to update a generation bit and a reference counter value included in the page cache used by the memory agent.

4. The computer system of claim 1, wherein to identify includes a translation of a cache coherency request into the memory command to the memory blade.

5. The computer system of claim 1, wherein the memory command includes at least one of a read command, a write command, or a swap command.

6. A computer implemented method comprising:

receiving a coherency request, using a memory agent, that identifies data residing on a memory blade to be accessed;

translating the coherency request, using the memory agent, into a memory command formatted based upon a protocol utilized by the memory blade; and

transmitting the memory command, using the memory agent, to the memory blade to access the data residing on the memory blade.

7. The computer implemented method of claim 6, further comprising updating a reference counter value, using the memory agent, that identifies a total number of times a virtual memory page, that includes the data, is accessed.

8. The computer implemented method of claim 6, further comprising setting a generation bit, using the memory agent, the generation bit identifying an instance during which a virtual memory page, that includes the data, is accessed.

9. The computer implemented method of claim 6, further comprising responding to the coherency request through accessing local memory in lieu of accessing the memory blade.

10. The computer implemented method of claim 6, further comprising clearing a generation bit, using the memory agent, after an expiration of a preset number of instances.

11. The computer implemented method of claim 6, further comprising identifying, using the memory agent, a virtual memory page that includes the data based upon a reference counter value associated with the virtual memory page, the identifying based upon a comparison of the reference counter value to a further reference counter value associated with a further virtual memory page.

12. The computer implemented method of claim 11, further comprising swapping the virtual memory page with the further memory page based upon the comparison of the reference counter value to the further reference counter value associated with the further virtual memory page.

13. The computer implemented method of claim 6, wherein the transmitting of the memory command includes packetizing the memory command using a Peripheral Component Interconnect Express (PCIe) protocol, Quick Path Interconnect (QPI), or a HyperTransport protocol.

14. A computer implemented method comprising:

identifying a virtual memory page, using a memory agent, the virtual memory page identified based upon, in part, a reference counter value;

getting data from the virtual memory page, using the memory agent, the virtual memory page less frequently accessed than a further virtual memory page based upon a comparison of the reference counter value to a further reference counter value associated with the further virtual memory page; and

storing the data into a write-back buffer using the memory agent.

15. The computer implemented method of claim 14, further comprising writing the write-back buffer to a memory module, using the memory agent, managed by a memory blade.