HIGH VOLTAGE DRAIN EXTENSION ON THIN BURIED OXIDE SOI

• US 20120104497A1
• Filed: 10/26/2011
• Published: 05/03/2012
• Est. Priority Date: 10/28/2010
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Denison, Marie, Hower, Philip L., Pendharkar, Sameer
• Granted Patent: US 9,806,190 B2
• Time in Patent Office: Days
• US Class Current: 257/348
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/1087 characterised by the contact structure of the substrate region, e.g. for controlling or preventing bipolar effect
• CPC Class Codes: H01L 29/7818 the other device being a pn-junction diode
• CPC Class Codes: H01L 29/7824 with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/861 Diodes

Abstract

An integrated circuit on an SOI substrate containing an extended drain MOS transistor with a through substrate diode in a drain (n-channel) or body region (p-channel) so that the drain or body region is coupled to the handle wafer through a p-n junction. An integrated circuit on an SOI substrate containing an extended drain MOS transistor with a through substrate diode in a drain (n-channel) or body region (p-channel) coupled to the handle wafer through a p-n junction, that is electrically isolated from the drain or body region. A process of forming an integrated circuit on an SOI substrate containing an extended drain MOS transistor with a through substrate diode in a drain (n-channel) or body region (p-channel).

Claims

1. An integrated circuit, comprising:

a silicon on insulator (SOI) substrate, including;

a handle wafer, of semiconductor material having a first conductivity type;

a buried oxide layer, of dielectric material, located on a top surface of said handle wafer; and

an SOI film of semiconductor material, located on a top surface of said buried oxide layer; and

an extended drain metal oxide semiconductor (MOS) transistor, including;

a region located in said SOI film, said region having an opposite conductivity type from said handle wafer; and

a through substrate diode located in said region, including;

a through substrate via extending from a top surface of said SOI film through said buried oxide layer into said handle wafer;

an electrically conductive via fill plug in said through substrate via, said via fill plug making electrical contact to said SOI film adjacent to said through substrate vias and to said handle wafer; and

a p-n junction adjacent to a boundary of said through substrate via.

2. The integrated circuit of claim 1, in which:

said handle wafer is p-type;

said extended drain MOS transistor is n-channel; and

said region is an n-type drain region.

3. The integrated circuit of claim 1, in which said p-n junction is located in said handle wafer adjacent to a bottom surface of said boundary of said through substrate via.

4. The integrated circuit of claim 1, in which said via fill plug includes polysilicon with a same conductivity type as said region.

5. The integrated circuit of claim 4, in which said SOI film includes a doped sidewall layer adjacent to said through substrate via, in which an average doping density in said doped sidewall layer is at least 40 percent more than an average doping density of said SOI film adjacent to said doped sidewall layer.

6. The integrated circuit of claim 1, in which:

said handle wafer is p-type;

said extended drain MOS transistor is p-channel; and

said region is an n-type body region.

7. The integrated circuit of claim 1, further including a through substrate contact located outside said extended drain MOS transistor.

8. An integrated circuit, comprising:

an SOI substrate, including;

a handle wafer, of semiconductor material having a first conductivity type;

a buried oxide layer, of dielectric material, located on a top surface of said handle wafer; and

an SOI film of semiconductor material, located on a top surface of said buried oxide layer; and

an extended drain MOS transistor, including;

a region located in said SOI film, said region having an opposite conductivity type from said handle wafer; and

a through substrate diode located in said region, including;

a through substrate via extending from a top surface of said SOI film through said buried oxide layer into said handle wafer;

a dielectric liner located on a sidewall of said through substrate via;

an implanted layer in said handle wafer located at a bottom surface of a boundary of said through substrate via, said implanted layer having said opposite conductivity type from said handle wafer;

an electrically conductive via fill plug in said through substrate via making electrical contact to said implanted layer, said via fill plug being electrically isolated from said SOI film by said dielectric liner; and

a p-n junction adjacent to said bottom surface of said boundary of said through substrate via, such that said via fill plug is electrically coupled to said handle wafer through said p-n junction.

9. The integrated circuit of claim 8, in which:

said handle wafer is p-type;

said extended drain MOS transistor is n-channel; and

said region is an n-type drain region.

10. The integrated circuit of claim 8, in which said via fill plug includes polysilicon.

11. The integrated circuit of claim 8, in which said dielectric liner includes silicon dioxide.

12. The integrated circuit of claim 8, in which:

said handle wafer is p-type;

said extended drain MOS transistor is p-channel; and

said region is an n-type body region.

13. A process of forming an integrated circuit, comprising steps:

providing an SOI substrate, said SOI substrate including;

a handle wafer, of semiconductor material having a first conductivity type;

a buried oxide layer, of dielectric material, formed on a top surface of said handle wafer; and

an SOI film of semiconductor material, formed on a top surface of said buried oxide layer; and

forming an extended drain metal oxide semiconductor (MOS) transistor, by a process including steps;

forming a region located in said SOI film, so that said region has an opposite conductivity type from said handle wafer; and

forming a through substrate diode in said region, by a process including steps;

forming a through substrate via extending from a top surface of said SOI film through said buried oxide layer into said handle wafer;

forming an electrically conductive via fill plug in said through substrate via, said via fill plug making electrical contact to said handle wafer; and

forming a p-n junction adjacent to a boundary of said through substrate via.

14. The process of claim 13, in which:

said handle wafer is p-type;

said extended drain MOS transistor is n-channel; and

said region is an n-type drain region.

15. The process of claim 13, in which said p-n junction is located in said handle wafer adjacent to a bottom surface of said boundary of said through substrate via.

16. The process of claim 15, in which said step of forming said through substrate diode further includes the step of forming a doped sidewall layer adjacent to said through substrate via, in which an average doping density in said doped sidewall layer is at least 40 percent more than an average doping density of said SOI film adjacent to said doped sidewall layer.

17. The process of claim 13, in which:

said step of forming said through substrate diode further includes the step of forming a dielectric liner on a sidewall of said through substrate via, so that said via fill plug is electrically isolated from said SOI film by said dielectric liner; and

said p-n junction is formed adjacent to a bottom surface of said boundary of said through substrate via, so that said via fill plug is electrically coupled to said handle wafer through said p-n junction.

18. The process of claim 13, in which:

said handle wafer is p-type;

said extended drain MOS transistor is p-channel; and

said region is an n-type body region.

19. The process of claim 13, further including the step of forming a through substrate contact outside said extended drain MOS transistor by a process including a step of forming a contact via through said SOI film and through said buried oxide layer, said contact via being formed concurrently with said through substrate via.

20. The process of claim 13, further including the step of forming a deep isolation trench outside said extended drain MOS transistor by a process including a step of forming an isolation trench in said SOI film, said isolation trench being formed concurrently with said through substrate via.