METHOD OF PRODUCING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE

• US 20120104502A1
• Filed: 03/24/2010
• Published: 05/03/2012
• Est. Priority Date: 03/31/2009
• Status: Abandoned Application

• Current Assignee: JX Nippon Mining & Metals Corporation (ENEOS Holdings, Inc.)
• Original Assignee: JX Nippon Mining & Metals Corporation (ENEOS Holdings, Inc.)
• Inventors: Imori, Toru, Ito, Junichi, Shibata, Tomohiro, Ikeda, Shuji, Momoi, Hajime
• Application Number:
  US13/260,948
• Publication Number:
  US 20120104502A1
• Time in Patent Office: Days
• US Class Current: 257/368
• CPC Class Codes: H01L 21/28537 Deposition of Schottky electrodes
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/66643 with source or drain regions formed by a Schottky barrier or a conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/7839 with Schottky drain or source contact

Abstract

Disclosed is a method of producing a semiconductor device, able to form a source/drain of a Schottky junction (FET) with simple steps and able to improve the device characteristics. A gate is formed on an element region defined in a silicon substrate layer by element isolation regions (first step), the silicon substrate is etched by self-alignment using the gate and the element isolation regions as masks (second step), and an insulating film is formed on the side surfaces of the gate (third step). Then, a metal film acting as the source/drain is selectively formed on the etching region of the silicon substrate by electroless plating (fourth step).

Claims

1-4. -4. (canceled)

5. A method for manufacturing a Schottky junction FET, comprising:

a first step of forming a gate on an element region defined in a surface layer of a silicon substrate by an element isolation region, the gate having an upper surface composed of a metal film covered with an insulating film;

a second step of etching the silicon substrate by self-alignment by using the gate and the element isolation region as masks;

a third step of adhering an insulating film onto an entirety of the silicon substrate, and etching back the insulating film by anisotropic etching, so as to form the insulating film on a side surface of the gate; and

a fourth step of immersing the silicon substrate into a plating solution, and selectively forming a metal film which is to be a source/drain, only on an etching region of the silicon substrate by an electroless plating method.

6. The method for manufacturing the Schottky junction FET according to claim 5, wherein the metal film of the source/drain is made of one type of metal selected from a group of gold, platinum, silver, copper, palladium, nickel, cobalt and ruthenium, or an alloy obtained by combining two types or more of the metal selected from the group with one another, or an alloy containing at least one type of the metal selected from the group.

7. A Schottky junction FET comprising:

a gate composed of a metal film, the gate being formed on an element region defined in a surface layer of a silicon substrate by an element isolation region; and

a source/drain formed on an etching region of the silicon substrate etched by using the gate and the element isolation region as masks,

wherein the source/drain has a metal film selectively formed by an electroless plating method.

8. The Schottky junction FET according to claim 7, wherein the metal film of the source/drain is made of one type of metal selected from a group of gold, platinum, silver, copper, palladium, nickel, cobalt and ruthenium, or an alloy obtained by combining two types or more of the metal selected from the group with one another, or an alloy containing at least one type of the metal selected from the group.