Capacitors in Integrated Circuits and Methods of Fabrication Thereof

• US 20120104552A1
• Filed: 10/27/2010
• Published: 05/03/2012
• Est. Priority Date: 10/27/2010
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Chae, Moosung, Moon, Bum Ki, Kim, Sunoo
• Granted Patent: US 8,618,635 B2
• Time in Patent Office: Days
• US Class Current: 257/535
• CPC Class Codes: H01G 4/002 Details
• CPC Class Codes: H01G 4/005 Electrodes
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 28/60 Electrodes
• CPC Class Codes: H01L 28/87 made by depositing layers, e.g. by depositing alternating conductive and insulating layers
• CPC Class Codes: H01L 28/90 having vertical extensions
• CPC Class Codes: H01L 28/92 made by patterning layers, e.g. by etching conductive layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

In one embodiment, a capacitor includes a first via level having first metal bars and first vias, such that the first metal bars are coupled to a first potential node. The first metal bars are longer than the first vias. Second metal bars and second vias are disposed in a second via level, the second metal bars are coupled to the first potential node. The second metal bars are longer than the second vias. The second via level is above the first via level and the first metal bars are parallel to the second metal bars. Each of the first metal bars has a first end, an opposite second end, and a middle portion between the first and the second ends. Each of the middle portions of the first metal bars and the second ends of the first metal bars do not contact any metal line.

Claims

1. A capacitor comprising:

a first via level comprising first metal bars and first vias, the first metal bars being coupled to a first potential node, the first metal bars having a longer length than the first vias; and

a second via level comprising second metal bars and second vias, the second metal bars coupled to the first potential node, the second via level being above the first via level, the second metal bars having a longer length than the second vias, wherein the first metal bars are parallel to the second metal bars, wherein each of the first metal bars has a first end, an opposite second end, and a middle portion between the first and the second ends, and wherein each of the middle portions of the first metal bars and the second ends of the first metal bars do not contact any metal line.

2. The capacitor of claim 1, wherein the first ends of the first metal bars contact a first metal line in a first metal level.

3. The capacitor of claim 1, wherein each of the second metal bars has a first end, an opposite second end, and a middle portion between the first and the second ends, wherein each of the middle portions of the second metal bars and the second ends of the second metal bars do not contact any metal line.

4. The capacitor of claim 3, wherein each of the first ends of the first metal bars contact a second metal line in a second metal level, and wherein each of the first ends of the second metal bars contact the second metal line.

5. The capacitor of claim 4, wherein each of the first ends of the first metal bars is coupled to each of the first ends of the second metal bars through the second metal line.

6. The capacitor of claim 3, wherein each of the first ends of the first metal bars contact a third metal bar disposed in the first via level, the third metal bar oriented perpendicular to the first metal bars.

7. The capacitor of claim 6, wherein each of the first ends of the second metal bars contact a fourth metal bar disposed in the second via level, the fourth metal bar oriented perpendicular to the second metal bars.

8. The capacitor of claim 7, further comprising a metal line disposed in a second metal level contacting the third metal bar and the fourth metal bar.

9. The capacitor of claim 1, further comprising:

third metal bars parallel to the first metal bars and disposed in the first via level, the third metal bars coupled to a second potential node, the third metal bars being capacitively coupled to the first metal bars, wherein each of the third metal bars has a first end, an opposite second end, and a middle portion between the first and the second ends, and wherein each of the middle portions of the third metal bars and the second ends of the third metal bars do not contact any metal line; and

fourth metal bars parallel to the second metal bars and disposed in the second via level, the fourth metal bars being coupled to the second potential node.

10. The capacitor of claim 9, wherein the first and the second metal bars form a first plate of the capacitor, and wherein the third and the fourth metal bars form a second plate of the capacitor.

11. The capacitor of claim 9, further comprising a first capacitor region formed by the first metal bars and the third metal bars, and a second capacitor region formed by the second metal bars and the fourth metal bars, wherein no metal line is disposed between the first capacitor region and the second capacitor region.

12. The capacitor of claim 1, wherein the first metal bars are laterally offset from the second metal bars.

13. The capacitor of claim 1, wherein the first metal bars extend into a first metal level, and wherein the first metal bars have the same shape within the first via level and the first metal level.

14. The capacitor of claim 1, wherein the first metal bars do not extend into any metal level.

15. A capacitor comprising:

first metal bars disposed in a first via level, the first metal bars being coupled to a first potential node;

second metal bars disposed in a second via level, the second metal bars being coupled to the first potential node, the second via level being above the first via level, wherein the first metal bars are parallel to the second metal bars; and

a insulating layer between the first metal bars and the second metal bars, wherein the first metal bars and the second metal bars are not coupled through a metal line disposed directly between the first metal bars and the second metal bars.

16. The capacitor of claim 15, further comprising:

third metal bars disposed in the first via level, the third metal bars being coupled to a second potential node; and

fourth metal bars disposed in the second via level, the fourth metal bars being coupled to the second potential node, the second via level being above the first via level, wherein the third metal bars are parallel to the fourth metal bars, wherein the third metal bars and the fourth metal bars are not coupled through a metal line disposed directly between them.

17. The capacitor of claim 16, wherein the first and the second metal bars form a first plate of the capacitor, and wherein the third and the fourth metal bars form a second plate of the capacitor.

18. The capacitor of claim 16, further comprising a first capacitor region formed by the first metal bars and the third metal bars, and a second capacitor region formed by the second metal bars and the fourth metal bars, wherein no metal line is disposed between the first capacitor region and the second capacitor region.

19. The capacitor of claim 15, wherein the first metal bars are parallel to the second metal bars, wherein each of the first metal bars has a first end, an opposite second end, and a middle portion between the first and the second ends, wherein each of the second metal bars has a first end, an opposite second end, and a middle portion between the first and the second ends, wherein each of the middle portions of the first metal bars and the second ends of the first metal bars do not contact any metal line, and wherein each of the middle portions of the second metal bars and the second ends of the second metal bars do not contact any metal line.

20. The capacitor of claim 19, further comprising:

a third metal bar perpendicular to the first metal bars, the third metal bar contacting each of the first ends of the first metal bars; and

a fourth metal bar perpendicular to the second metal bars, the fourth metal bar contacting each of the first ends of the second metal bars.

21. A semiconductor structure comprising:

a first via level comprising first metal bars and first vias, the first metal bars having a longer length than the first vias; and

a second via level comprising second metal bars and second vias, the second via level being above the first via level, wherein the first metal bars and the second metal bars are both oriented along a first direction, wherein the second metal bars have a longer length along the first direction than the second vias, and wherein the first metal bars and the second metal bars are laterally offset in a second direction perpendicular to the first direction.

22. The semiconductor structure of claim 21, wherein no metal line is disposed between the first metal bars and the second metal bars.

23. The semiconductor structure of claim 21, wherein the offset is about 5% of a width of the first metal bars in the second direction.

24. The semiconductor structure of claim 21, wherein the offset is about 5% to about 20% of a width of the first metal bars in the second direction.

25. A method of fabricating a semiconductor device, the method comprising:

depositing a first insulating layer over a workpiece;

forming first metal bars in the first insulating layer over a first region of the workpiece;

forming a second insulating layer over the first insulating layer;

forming metal lines over a second region of the workpiece and not directly over the first metal bars;

forming a third insulating layer over the second insulating layer; and

forming second metal bars in the third insulating layer over the first region of the workpiece.

26. The method of claim 25, wherein the first metal bars are parallel to the second metal bars, wherein each of the first metal bars has a first end, an opposite second end, and a middle portion between the first and the second ends, and wherein each of the middle portions of the first metal bars and the second ends of the first metal bars do not contact any metal line.

27. The method of claim 26, wherein each of the second metal bars has a first end, an opposite second end, and a middle portion between the first and the second ends, wherein each of the middle portions of the second metal bars and the second ends of the second metal bars do not contact any metal line, wherein each of the first ends of the first metal bars contact a second metal line in a second metal level, and wherein each of the first ends of the second metal bars contact the second metal line.

28. The method of claim 25, wherein forming first metal bars comprises:

forming openings for first metal bars in the first insulating layer; and

filling the openings for first metal bars with a conductive fill material.

29. The method of claim 25, further comprising:

forming a third metal bar in the first insulating layer, the third metal bar oriented perpendicular to the first metal bars, wherein each of the first metal bars contact the third metal bar; and

forming a fourth metal bar in the first insulating layer, the fourth metal bar oriented perpendicular to the second metal bars, wherein each of the second metal bars contact the fourth metal bar.

30. The method of claim 29, further comprising a metal line disposed in the second insulating layer, the metal line contacting the third metal bar and the fourth metal bar.