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Digital Phase-Locked Loop Architecture

  • US 20120105120A1
  • Filed: 04/07/2010
  • Published: 05/03/2012
  • Est. Priority Date: 04/14/2009
  • Status: Active Grant
First Claim
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1. A phase-locked loop circuit comprising:

  • an oscillator configured to generate an output signal;

    an input for receiving a reference clock signal;

    a delay cell configured to delay the reference clock signal to generate a delayed reference clock signal;

    a phase comparator configured to generate a quantised signal indicative of the phase difference between the output signal and the reference clock signal;

    an integrator configured to integrate the quantised signal to form an integrated signal;

    a first feedback path configured to control the phase and/or frequency of the oscillator in dependence on the integrated signal; and

    a second feedback path configured to adjust the delay applied by the delay cell in dependence on the integrated signal.

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