METHOD AND APPARATUS FOR OPTIMIZING DRIVER LOAD IN A MEMORY PACKAGE

• US 20120106228A1
• Filed: 11/03/2011
• Published: 05/03/2012
• Est. Priority Date: 11/03/2010
• Status: Active Grant

• Current Assignee: Netlist, Inc.
• Original Assignee: Netlist, Inc.
• Inventors: Lee, Hyun
• Granted Patent: US 8,787,060 B2
• Time in Patent Office: Days
• US Class Current: 365/63
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: G11C 5/066 Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
• CPC Class Codes: G11C 7/1057 Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/1084 Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Abstract

An apparatus is provided that includes a plurality of array dies and at least two die interconnects. The first die interconnect is in electrical communication with a data port of a first array die and a data port of a second array die and not in electrical communication with data ports of a third array die. The second die interconnect is in electrical communication with a data port of the third array die and not in electrical communication with data ports of the first array die and the second array die. The apparatus includes a control die that includes a first data conduit configured to transmit a data signal to the first die interconnect and not to the second die interconnect, and at least a second data conduit configured to transmit the data signal to the second die interconnect and not to the first die interconnect.

Claims

1. A memory package, comprising:

a plurality of array dies having data ports;

at least a first die interconnect and a second die interconnect, the first die interconnect in electrical communication with at least one data port of a first array die of the plurality of array dies and at least one data port of a second array die of the plurality of array dies and not in electrical communication with the data ports of at least a third array die of the plurality of array dies, the second die interconnect in electrical communication with at least one data port of the third array die and not in electrical communication with the data ports of the first array die and the data ports of the second array die; and

a control die comprising at least a first data conduit configured to transmit a data signal to the first die interconnect and to not transmit the data signal to the second die interconnect, and at least a second data conduit configured to transmit the data signal to the second die interconnect and to not transmit the data signal to the first die interconnect.

2. The memory package of claim 1, wherein the first data conduit and the second data conduit are configured to receive the data signal from a common source as one another.

3. The memory package of claim 1, wherein a first load on the first data conduit comprises a load of the first die interconnect, a load of the first array die, and a load of the second array die, and wherein a second load on the second data conduit comprises a load of the second die interconnect and a load of the third array die.

4. The memory package of claim 3, wherein a difference between the first load and the second load is less than a load that would be on the first data conduit upon the first die interconnect being placed in electrical communication with at least one data port of each of the array dies of the plurality of array dies.

5. The memory package of claim 3, wherein:

the first load is less than a load that would be on the first data conduit upon the first die interconnect being placed in electrical communication with at least one data port of each of the array dies of the plurality of array dies; and

the second load is less than a load that would be on the second data conduit upon the second die interconnect being placed in electrical communication with at least one data port of each of the array dies of the plurality of array dies.

6. The memory package of claim 1, wherein the first die interconnect comprises a first conducting rod and wherein the second die interconnect comprises a second conducting rod.

7. The memory package of claim 1, wherein one of the first die interconnect and the second die interconnect is in electrical communication with at least one data port of a fourth array die of the plurality of array dies and the other one of the first die interconnect and the second die interconnect is not in electrical communication with the data ports of the fourth array die.

8. The memory package of claim 1, wherein the first die interconnect is configured to transmit signals to the first array die and the second array die, and to receive signals from the first array die and the second array die, and the second die interconnect is configured to transmit signals to the third array die and to receive signals from the third array die.

9. The memory package of claim 1, further comprising at least a third die interconnect and a fourth die interconnect, the third die interconnect in electrical communication with at least one data port of the first array die and at least one data port of the second array die and not in electrical communication with the data ports of at least the third array die, the fourth die interconnect in electrical communication with at least one data port of the third array die and not in electrical communication with the data ports of the first array die and the data ports of the second array die.

10. The memory package of claim 9, wherein the first die interconnect is configured to transmit signals to the first array die and the second array die, the second die interconnect is configured to transmit signals to the third array die, the third die interconnect is configured to receive signals from the first array die and the second array die, and the fourth die interconnect is configured to receive signals from the third array die.

33. The memory module of claim 29, wherein at least one of the plurality of DRAM packages comprises the memory package of claim 1.

11. A memory package, comprising:

a plurality of array dies having ports;

at least a first die interconnect and a second die interconnect, the first die interconnect in electrical communication with at least one port of a first array die of the plurality of array dies and at least one port of a second array die of the plurality of array dies and not in electrical communication with the ports of at least a third array die of the plurality of array dies, the second die interconnect in electrical communication with at least one port of the third array die and not in electrical communication with the ports of the first array die and the ports of the second array die; and

a control die comprising at least a first conduit configured to transmit a signal to the first die interconnect and to not transmit the signal to the second die interconnect, and at least a second conduit configured to transmit the signal to the second die interconnect and to not transmit the signal to the first die interconnect,

wherein a first load on the first conduit comprises a load of the first die interconnect, a load of the first array die, and a load of the second array die, and

wherein a second load on the second conduit comprises a load of the second die interconnect and a load of the third array die.

12. The memory package of claim 11, wherein a difference between the first load and the second load is less than a load that would be on the first conduit upon the first die interconnect being placed in electrical communication with at least one port of each of the array dies of the plurality of array dies.

13. The memory package of claim 11, wherein:

the first load is less than a load that would be on the first conduit upon the first die interconnect being placed in electrical communication with at least one port of each of the array dies of the plurality of array dies; and

the second load is less than a load that would be on the second conduit upon the second die interconnect being placed in electrical communication with at least one port of each of the array dies of the plurality of array dies.

14. The memory package of claim 11, wherein the first die interconnect comprises a first conducting rod and wherein the second die interconnect comprises a second conducting rod.

15. The memory package of claim 11, wherein:

the first conduit comprises at least a first driver, and

the second conduit comprises at least a second driver.

16. The memory package of claim 15, wherein the first driver and the second driver are configured to receive the signal from a common source as one another.

17. The memory package of claim 16, wherein the signal comprises a data signal.

18. The memory package of claim 16, wherein the signal comprises at least one of the following:

a command signal, an address signal, and a control signal.

19. The memory package of claim 16, further comprising a third driver and a fourth driver, wherein the third driver is configured to drive a first signal received from the first die interconnect, and wherein the fourth driver is configured to drive a second signal received from the second die interconnect.

34. The memory module of claim 29, wherein at least one of the plurality of DRAM packages comprises the memory package of claim 11.

20. A method for optimizing load in a memory package comprising a plurality of array dies, at least a first die interconnect and a second die interconnect, and a control die comprising at least a first driver and a second driver, the first driver configured to drive a signal along the first die interconnect, and the second driver configured to drive the signal along the second die interconnect, the method comprising:

selecting a first subset of array dies of the plurality of array dies and a second subset of array dies of the plurality of array dies, wherein the first subset of array dies and the second subset of array dies are exclusive of one another and are selected to balance a load on the first driver and on the second driver based at least in part on array die loads of array dies of the plurality of array dies and at least in part on die interconnect segment loads of segments of at least the first die interconnect and the second die interconnect;

forming electrical connections between the first die interconnect and the first subset of array dies; and

forming electrical connections between the second die interconnect and the second subset of array dies.

21. The method of claim 20, further comprising:

selecting a first driver size for the first driver based, at least in part, on the load on the first driver; and

selecting a second driver size for the second driver based, at least in part, on the load on the second driver.

22. The method of claim 21, wherein the first driver size and the second driver size are both less than a driver size sufficient to drive the signal along a die interconnect in electrical communication with each of the plurality of array dies with a less than predetermined signal degradation.

23. The method of claim 20, wherein each array die of the plurality of array dies comprises a substantially equal array die load.

24. The method of claim 20, wherein each segment of the first die interconnect and the second die interconnect comprises a substantially equal die interconnect segment load.

25. The method of claim 20, wherein the segments of the die interconnect comprise one or more portions of a die interconnect between two adjacent array dies.

26. The method of claim 20, wherein the segments of the die interconnect comprise one or more portions of a die interconnect between the control die and an adjacent array die.

27. The method of claim 20, wherein the first subset of array dies comprises at least two array dies.

28. The method of claim 20, wherein balancing the load on the first driver and the load on the second driver comprises minimizing a load difference between the first driver and the second driver.

29. A memory module comprising:

a register device configured to receive command/address signals from a memory control hub and to generate data path control signals; and

a plurality of DRAM packages, each DRAM package comprising;

a control die comprising a plurality of command/address buffers and a data path control circuit configured to control command/address time slots and data bus time slots, the control die configured to receive data signals from the memory control hub, the data path control signals from the register device, and command/address signals from the register device; and

a plurality of DDR DRAM dies operatively coupled to the control die to receive the data signals from the control die,

wherein the memory module is selectively configurable into at least two operational modes comprising;

a first operational mode in which the register device generates the data path control signals, and the control die uses the data path control signals to operate the data path control circuit; and

a second operational mode in which the control die operates the data path control circuit to provide the command/address signals to the plurality of DDR DRAM dies without decoding the command/address signals.

30. The memory module of claim 29, wherein the register device is further configured to perform rank multiplication.

31. The memory module of claim 29, wherein the memory module does not perform rank multiplication while operating in the second operational mode.

32. The memory module of claim 29, wherein the control die is further configured to perform rank multiplication.