BANDWIDTH INDICATION IN RTS/CTS FRAMES

• US 20120106426A1
• Filed: 11/01/2010
• Published: 05/03/2012
• Est. Priority Date: 11/01/2010
• Status: Active Grant

• Current Assignee: Cisco Technology, Inc. (Cisco Systems, Inc.)
• Original Assignee: Cisco Technology, Inc. (Cisco Systems, Inc.)
• Inventors: HART, Brian, Hedayat, Ahmadreza
• Granted Patent: US 8,873,384 B2
• Time in Patent Office: Days
• US Class Current: 370/312
• CPC Class Codes: H04L 1/0054 Maximum-likelihood or sequential decoding, e.g. Viterbi, Fano, ZJ algorithms
• CPC Class Codes: H04L 1/0061 Error detection codes
• CPC Class Codes: H04L 5/001 the frequencies being arranged in component carriers
• CPC Class Codes: H04L 5/0064 Rate requirement of the data, e.g. scalable bandwidth, data priority
• CPC Class Codes: H04L 5/0092 Indication of how the channel is divided
• CPC Class Codes: H04L 5/1438 Negotiation of transmission parameters prior to communication modified according to link quality H04L1/0001
• CPC Class Codes: H04W 28/20 Negotiating bandwidth

Abstract

Disclosed in an example embodiment is an apparatus comprising a transmitter and processing logic coupled with the transmitter. The processing logic is configured to send data via the transmitter. The processing logic generates a request to send frame. The processing logic encodes data representative of a bandwidth parameter set in the request to send frame. The processing logic transmits the request to send frame via the transmitter.

Claims

1. An apparatus, comprising

a transmitter;

processing logic coupled with the transmitter, the processing logic is configured to send data via the transmitter;

wherein the processing logic generates a request to send frame;

wherein the processing logic encodes data representative of a bandwidth parameter set in the request to send frame; and

wherein the processing logic transmits the request to send frame via the transmitter.

2. The apparatus of claim 1, wherein the request to send frame comprises data representative of a scrambler seed;

and

wherein the processing logic encodes the data representative of a bandwidth parameter set into the scrambler seed or scrambler field.

3. The apparatus of claim 2, wherein processing logic further encodes data representative of whether the transmitter is capable of static or dynamic bandwidth into the data representative of the scrambler seed.

4. The apparatus of claim 1, wherein the processing logic further includes in the request to send frame, predefined data indicating that the frame contains a bandwidth parameter set.

5. The apparatus of claim 4, wherein the request to send frame further comprises a transmitter address field;

and

wherein the processing logic sets a multicast bit in the transmitter address field to indicate that the frame contains a bandwidth parameter set.

6. The apparatus of claim 1, wherein the request to send frame further comprises a Duration field;

wherein the processing logic performs a hash on the Duration field; and

wherein the processing logic includes the data representative of a bandwidth parameter set at a location in the frame based on the hash of the Duration field.

7. The apparatus of claim 1, wherein the request to send frame further includes pad bits;

and

wherein the processing logic encodes the data representative of a bandwidth parameter set into the pad bits.

8. The apparatus of claim 7, wherein the request to send frame further includes service bits, a payload, and tail bits;

wherein the processing logic scrambles the service bits, payload, tail bits, and bits;

wherein the processing logic overwrites the tail bits with a predefined value;

wherein the processing logic modifies a portion of the pad bits to include data representative of a bandwidth parameter set; and

wherein the processing logic encodes the service bits, payload, tail bits, and pad after modifying the pad bits to include the data representative of a bandwidth parameter set.

9. The apparatus of claim 7, wherein the processing logic encodes ten pad bits so that they can be decoded in reverse time using bit-reversed convolutional code polynomials.

10. The apparatus of claim 9, wherein the processing logic includes data to distinguish from a legacy request to send in the ten pad bits.

11. The apparatus of claim 10, wherein the ten pad bits further includes a cyclic redundancy code that protects the data representative of a bandwidth parameter set in the data to distinguish from a legacy request to send and/or to ensure that bit errors do not lead to an erroneous understanding of the bandwidth indication or static/dynamic indication.

12. The apparatus of claim 1, wherein the processing logic modifies pad bit to include the bandwidth parameter set after the pad bits are encoded and punctured.

13. The apparatus of claim 12, wherein the processing logic modifies at least five bits of the pad bits of the request to send frame to include the bandwidth parameter set.

14. The apparatus of claim 13, wherein the processing logic includes multiple additional copies of the at least four bits of the modified pad bits.

15. An apparatus, comprising

a receiver;

processing logic coupled with the transmitter, the processing logic is configured to receive data via the receiver;

wherein the processing logic receives a request to send frame; and

wherein the processing logic obtains data representative of a bandwidth parameter set from the request to send frame.

16. The apparatus of claim 15, wherein the request to send frame comprises data representative of a scrambler seed;

and

wherein the processing logic decodes the data representative of a bandwidth parameter set from the data representative of the scrambler seed.

17. The apparatus of claim 16, wherein processing logic further decodes data representative of the bandwidth parameter set from the data representative of the scrambler seed.

18. The apparatus of claim 15, wherein the processing logic determines from a transmitter address field in the request to send frame data that the request to send frame comprises data representative of a bandwidth parameter set.

19. The apparatus of claim 18, further comprising a transmitter

wherein the processing logic determines from a multicast bit set in the transmitter address that the request to send contains data representative of a bandwidth parameter set;

wherein the processing logic is responsive to receiving the request to send frame to respond with a clear to send frame;

wherein the processing logic copies the transmitter from the request to send frame into a receiver address of the clear to send frame;

wherein the processing logic sets a multicast bit in the receiver address field of the clear to send frame to unicast; and

wherein the clear to send frame is sent via the transmitter.

20. The apparatus of claim 15, wherein the request to send frame further comprises a Duration field;

wherein the processing logic performs a hash on the Duration field; and

wherein the processing logic determines the location of the data representative of a bandwidth parameter set based on the hash of the Duration field.

21. The apparatus of claim 15, wherein the request to send frame further includes pad bits;

and

wherein the processing logic obtains the data representative of a bandwidth parameter set from the pad bits.

22. The apparatus of claim 21, wherein the request to send frame further includes tail bits;

wherein the processing logic decodes the tail bits;

wherein the processing logic obtains the bandwidth parameter set from a predetermined location within the pad bits.

23. The apparatus of claim 21, wherein the processing logic obtains the data representative of the bandwidth parameter set from the pad bits before decoding the pad bits.

24. The apparatus of claim 21, wherein the processing logic obtains the data representative of a bandwidth parameter set from a sequence of at least four bits in the pad bits of the request to send frame.

25. The apparatus of claim 21, further comprising a transmitter;

wherein the processing logic is responsive to receiving the request to send frame to respond with a clear to send frame, the clear to send frame comprising tail bits;

wherein the processing logic encodes data representative of the bandwidth parameter set in the pad bits of the clear to send frame;

wherein the clear to send frame with the encoded data representative of the bandwidth parameter set in the pad bits is sent via the transmitter.