ROUTER AND SWITCH ARCHITECTURE

• US 20120106562A1
• Filed: 10/26/2011
• Published: 05/03/2012
• Est. Priority Date: 10/28/2010
• Status: Active Grant

• Current Assignee: Rusnano Joint Stock Company
• Original Assignee: Compass Electro Optical Systems Ltd.
• Inventors: Laor, Michael, Oren, Eyal, Miliavsky, Vladimir
• Granted Patent: US 9,363,173 B2
• Time in Patent Office: Days
• US Class Current: 370/401
• CPC Class Codes: H04L 45/60 Router architectures
• CPC Class Codes: H04L 49/10 characterised by the switching fabric construction
• CPC Class Codes: H04L 49/3009 Header conversion, routing tables or routing tags

Abstract

A packet switching system for a packet transfer network, the system having an architecture including a plurality of line cards, each including an ingress path pipeline, with processing elements, and an egress buffer, and an electro-optical In/Out (IO) interconnect coupling the line cards to one another in a full mesh connectivity, in the absence of a switch fabric, wherein the ingress path pipeline of each line card is coupled by means of the electro-optical IO interconnect to the egress buffer of each of the plurality of line cards.

Claims

1. A packet switching system for a packet transfer network comprising:

a plurality of line cards, each line card comprising an ingress path pipeline and an egress buffer; and

an electro-optical In/Out (IO) interconnect coupling the ingress path pipeline of each line card to the egress buffer of the other line cards;

wherein the ingress path pipeline of each line card is configured to perform ingress processing and partial egress processing on a packet received from the packet transfer network.

2. The architecture according to claim 1, wherein said electro-optical IO interconnect includes a plurality of integrated circuit chips, each integrated circuit chip having a plurality of light sources for transferring processed data from one of said line cards to another of said line cards via a plurality of photo detectors.

3. The architecture according to claim 1, wherein the said ingress path pipeline of each line card includes elements for processing the packet and for determining a destination address of the packet.

4. The architecture according to claim 1, wherein said electro-optical IO interconnect includes:

a CMOS chip with logic circuitry coupled to a matrix of vertical-cavity surface-emitting lasers (VCSELs) and to a matrix of Photo Detectors (PDs);

wherein said CMOS circuitry includes interface circuitry between the logic circuitry on said CMOS chip and said matrix of VCSELs, and between the logic circuitry on said CMOS chip and said PDs.

5. The architecture according to claim 4, wherein said electro-optical IO interconnect further includes:

a first matrix of passive optical elements coupled to said matrix of VCSELs; and

a second matrix of passive optical elements coupled to said matrix of PDs;

wherein the PDs are in optical communication with the VCSELs; and

wherein said PD and VCSEL matrixes are mechanically and thermally isolated from the first and second matrixes of passive optical elements.

6. The architecture according to claim 2, wherein each logical integrated circuit chip comprises an Electro-Optical analog interface.

7. The architecture according to claim 2, wherein each said integrated circuit chip is a CMOS chip.

8. The architecture according to any of the preceding claims, wherein said electro-optical IO interconnect includes a congestion-free path from the ingress path pipeline of each line card to the egress buffer of each line card regardless of the type of traffic arriving at the line cards from the packet transfer network.

9. A method of creating a packet switching system for a packet transfer network comprising:

providing a plurality of line cards, each line card comprising an ingress path pipeline and an egress buffer;

coupling the ingress path pipeline of each line card to the egress buffer of the other line cards by an electro-optical In/Out (IO) interconnect;

wherein the ingress path pipeline is configured to perform ingress processing and partial egress processing on a packet received from the packet transfer network.

10. The method according to claim 9, wherein the electro-optical IO interconnect includes a plurality of integrated circuit chips, each integrated circuit chip having a plurality of light sources for transferring processed data from one of said line cards to another of said line cards via a plurality of photo detectors.

11. The method according to claim 9, wherein the electro-optical IO interconnect comprises a CMOS chip with logic circuitry, a matrix of VCSELs, and a matrix of Photo Detectors (PDs), the method further comprising:

coupling the CMOS chip with logic circuitry to the matrix of VCSELs, and to the matrix of PDs;

providing, an interface circuitry between the logic circuitry on said CMOS chip and said VCSELs, and between the logic circuitry on said CMOS chip and said PDs.

12. The method according to claim 11, further comprising:

coupling a first matrix of passive optical elements to said matrix of VCSELs;

coupling a second matrix of passive optical elements to said matrix of PDs;

wherein said PDs are in optical communication with the VCSELs in another said CMOS chip; and

wherein the PD and VCSEL matrixes are mechanically and thermally isolated from the first and second matrixes of passive optical elements.

13. A method of packet switching through a packet switching network comprising:

receiving a packet in an ingress path pipeline in a first line card;

performing ingress processing and partial egress processing in said ingress path pipeline, including determining a destination address of said packet;

transferring said processed packet to an egress buffer on a second line card via an electro-optical In/Out (IO) interconnect connecting the ingress path pipeline of each line card to an egress buffer on each said line card; and

performing additional egress processing in said egress buffer.

14. The method according to claim 13, wherein

said step of performing ingress processing includes attaching an internal data structure to said packet indicating additional processing required in the egress;

and

said step of performing additional egress processing includes performing said additional processing indicated in said internal data structure.

15. The method according to claim 13, wherein said step of transferring is performed at a speed up of an integer number.

16. The method according to claim 15, wherein the integer number is equal to the sum of all the line card output speeds.

17. The method according to claim 13, wherein said ingress processing includes light modulation.

18. The method according to claim 13, wherein said egress buffer receives packets from a plurality of said ingress pipelines simultaneously.

19. The method according to claim 13, wherein said egress buffer receives packets from all of said ingress pipelines simultaneously.

20. The method according to claim 13, further comprising transferring said packet over a permanent congestion-free path through said electro-optical IO interconnect to said egress buffer after said partial egress processing.