METHOD FOR FABRICATION OF A SEMICONDUCTOR DEVICE AND STRUCTURE

• US 20120107967A1
• Filed: 12/08/2011
• Published: 05/03/2012
• Est. Priority Date: 07/30/2010
• Status: Active Grant

• Current Assignee: Monolithic 3D, Inc.
• Original Assignee: Monolithic 3D, Inc.
• Inventors: Or-Bach, Zvi, Sekar, Deepak C., Cronquist, Brian, Beinglass, Israel, de Jong, Jan Lodewijk
• Granted Patent: US 8,709,880 B2
• Time in Patent Office: Days
• US Class Current: 438/4
• CPC Class Codes: G11C 17/14 in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
• CPC Class Codes: H01L 21/76254 with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 21/8226 comprising merged transistor logic or integrated injection logic
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 2223/5442 comprising non digital, non alphanumeric information, e.g. symbols
• CPC Class Codes: H01L 2223/54426 for alignment
• CPC Class Codes: H01L 2223/54453 for use prior to dicing
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45147 Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/80001 by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 2225/06589 Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/5252 : comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
• CPC Class Codes: H01L 23/528 : Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/53214 : the principal metal being aluminium
• CPC Class Codes: H01L 23/53228 : the principal metal being copper
• CPC Class Codes: H01L 23/544 : Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 24/14 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/18 : the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 27/0207 : Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0688 : Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/0694 : comprising components formed on opposite sides of a semiconductor substrate
• CPC Class Codes: H01L 27/088 : the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/092 : complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/11803 : using field effect technology
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00011 : Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01066 : Dysprosium [Dy]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/12032 : Schottky diode
• CPC Class Codes: H01L 2924/12036 : PN diode
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/1301 : Thyristor
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13062 : Junction field-effect transistor [JFET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15788 : Glasses, e.g. amorphous oxides, nitrides or fluorides
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H03K 17/687 : the devices being field-effect transistors
• CPC Class Codes: H03K 19/0948 : using CMOS or complementary insulated gate field-effect transistors
• CPC Class Codes: H03K 19/177 : arranged in matrix form
• CPC Class Codes: H10B 10/00 : Static random access memory [SRAM] devices
• CPC Class Codes: H10B 10/125 : the MOSFET being a thin film transistor [TFT]
• CPC Class Codes: H10B 12/05 : Making the transistor
• CPC Class Codes: H10B 12/053 : the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/50 : Peripheral circuit region structures
• CPC Class Codes: H10B 20/00 : Read-only memory [ROM] devices
• CPC Class Codes: H10B 20/25 : One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links

Abstract

A method of manufacturing a semiconductor wafer, the method including: providing a first monocrystalline layer including first transistors and interconnecting metal layers to perform at least one first electronic function; providing a second monocrystalline layer on top of the metal layers, wherein the second monocrystalline layer includes second transistors to perform at least one second electronic function and substituting the at least one first electronic function with the at least one second electronic function.

Claims

1. A method of manufacturing a semiconductor device, the method comprising:

providing a first monocrystalline layer comprising first transistors and interconnecting metal layers to perform at least one first electronic function;

providing a second monocrystalline layer on top of said metal layers, wherein said second monocrystalline layer comprises second transistors to perform at least one second electronic function; and

substituting the at least one first electronic function with the at least one second electronic function.

2. The method according to claim 1 wherein:

at least one of the second transistors overlays at least a portion of the first transistors.

3. The method according to claim 2 wherein said second electronic function is substantially equivalent to said first electronic function.

4. The method according to claim 1, wherein said second electronic function is substituted for the first electronic function by using a direct write eBeam.

5. The method according to claim 1, wherein said substituting repairs the first electronic function of said semiconductor device.

6. The method according to claim 1, further comprising testing said first electronic function performed by said first transistors prior to said substituting.

7. The method according to claim 1, wherein said substituting comprises using an electrical programmable switch.

8. The method according to claim 1, wherein said substituting comprises configuring at least a portion of the semiconductor to selectively perform the first electronic function or the second electronic function.

9. A method of manufacturing a semiconductor device, the method comprising:

providing a first monocrystalline layer comprising first transistors and interconnecting metal layers;

providing a second monocrystalline layer on top of said metal layers, wherein said second monocrystalline layer comprises second transistors;

etching at least a portion of a repeating circuit structure comprising at least one of said first or second transistors.

10. The method according to claim 9 wherein:

said repeating circuit structure comprises a memory cell.

11. The method according to claim 9 wherein:

said repeating circuit structure comprises a programmable logic cell.

12. The method according to claim 9 wherein:

said repeating circuit structure comprises a customizable logic cell.

13. The method according to claim 9 wherein:

said portion comprises at least one fully processed transistor.

14. The method according to claim 9 wherein:

said portion comprises at least one fully processed metal line.

15. A method of manufacturing a semiconductor device, the method comprising:

providing a first monocrystalline layer comprising first transistors and interconnecting metal layers;

providing a second monocrystalline layer on top of said metal layers, wherein said second monocrystalline layer comprises second transistors;

subsequently interconnecting at least two repeating circuit tiles, each circuit tile comprising at least one of said first or second transistors;

wherein

said interconnecting is performed a first time to connect a first portion of said circuit tiles and a second time to connect a second portion of said circuit tiles, and wherein said first portion is different from said second portion.

16. The method according to claim 15 wherein:

said circuit tiles comprise a memory circuit.

17. The method according to claim 15 wherein:

said circuit tiles comprise a programmable logic circuit.

18. The method according to claim 15 wherein:

said circuit tiles comprise a customizable logic circuit.

19. The method according to claim 15 wherein:

said circuit tiles comprise a micro controller unit (MCU).

20. A method of manufacturing a semiconductor device, the method comprising:

providing a first monocrystalline layer comprising first transistors;

providing a second monocrystalline layer on top of said first monocrystalline layer, wherein said second monocrystalline layer comprises second transistors; and

annealing said first monocrystalline layer and said second monocrystalline layer.

21. The method according to claim 20 wherein:

said annealing activates dopants of at least one of said first or second transistors.

22. The method according to claim 20 wherein:

at least a portion of said first transistors comprise memory cells.

23. The method according to claim 20 wherein:

at least a portion of said first transistors and said second transistors comprise memory cells.