METHOD FOR MANUFACTURING THIN FILM TRANSISTOR SUBSTRATE

• US 20120108018A1
• Filed: 03/16/2010
• Published: 05/03/2012
• Est. Priority Date: 07/24/2009
• Status: Active Grant

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Okabe, Tohru, Nishiki, Hirohiko, Chikama, Yoshimasa, Hara, Takeshi
• Granted Patent: US 8,481,373 B2
• Time in Patent Office: Days
• US Class Current: 438/158
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

A method for manufacturing a thin film transistor substrate includes a step of forming a gate electrode (11a) and a first interconnect on a substrate (10), a step of forming a gate insulating film (12a) having a contact hole at a position overlapping the first interconnect, a step of forming a source electrode (13a) and a drain electrode (13b) overlapping the gate electrode (11a) and separated apart from each other, and a second interconnect connected via the contact hole to the first interconnect, a step of successively forming an oxide semiconductor film (14) and a second insulating film (15), and thereafter, patterning the second insulating film (15) to form an interlayer insulating film (15a), and a step of reducing the resistance of the oxide semiconductor film (14) exposed through the interlayer insulating film (15a) to form a pixel electrode (14b).

Claims

1. A method for manufacturing a thin film transistor substrate, comprising:

a gate layer formation step of forming a gate electrode and a first interconnect on a substrate;

a gate insulating film formation step of forming a first insulating film covering the gate electrode and the first interconnect, and thereafter, patterning the first insulating film to form a contact hole at a position overlapping the first interconnect, thereby forming a gate insulating film;

a source layer formation step of forming a conductive film covering the gate insulating film, and thereafter, patterning the conductive film to form a source electrode and a drain electrode overlapping the gate electrode and separated apart from each other, and a second interconnect intersecting the first interconnect and connected via the contact hole to the first interconnect;

an interlayer insulating film formation step of successively forming an oxide semiconductor film and a second insulating film covering the source electrode, the drain electrode, and the second interconnect, and thereafter, patterning the second insulating film to form an interlayer insulating film; and

a pixel electrode formation step of reducing the resistance of the oxide semiconductor film exposed through the interlayer insulating film to form a pixel electrode.

6. The method of claim 1, wherein

in the pixel electrode formation step, the oxide semiconductor film exposed through the interlayer insulating film is treated with a plasma.

7. The method of claim 1, wherein

in the pixel electrode formation step, an impurity is implanted into the oxide semiconductor film exposed through the interlayer insulating film.

8. The method of claim 1, wherein

in the pixel electrode formation step, a thickness of the oxide semiconductor film exposed through the interlayer insulating film is reduced by etching.

9. The method of claim 1, wherein

the second interconnect is a source line conductive to the source electrode, and

the first interconnect is a first connection line configured to connect to the source line.

10. The method of claim 1, wherein

the first interconnect is a gate line conductive to the gate electrode, and

the second interconnect is a second connection line configured to connect to the gate line.

2. A method for manufacturing a thin film transistor substrate, comprising:

a gate layer formation step of forming a gate electrode and a first interconnect on a substrate;

a gate insulating film formation step of successively forming a first insulating film and an oxide semiconductor film covering the gate electrode and the first interconnect, and thereafter, patterning the multilayer film of the first insulating film and the oxide semiconductor film to form a contact hole at a position overlapping the first interconnect, thereby forming a gate insulating film;

a source layer formation step of forming a conductive film covering the oxide semiconductor film, and thereafter, patterning the conductive film to form a source electrode and a drain electrode overlapping the gate electrode and separated apart from each other, and a second interconnect intersecting the first interconnect and connected via the contact hole to the first interconnect;

an interlayer insulating film formation step of forming a second insulating film covering the source electrode, the drain electrode, and the second interconnect, and thereafter, patterning the second insulating film to form an interlayer insulating film; and

a pixel electrode formation step of reducing the resistance of the oxide semiconductor film exposed through the interlayer insulating film to form a pixel electrode.

3. The method of claim 2, wherein

in the gate layer formation step, the gate electrode is made wide enough to reach a boundary between the drain electrode formed in the source layer formation step and the pixel electrode formed in the pixel electrode formation step.

4. A method for manufacturing a thin film transistor substrate, comprising:

a gate layer formation step of forming a gate electrode and a first interconnect on a substrate;

a gate insulating film formation step of successively forming a first insulating film and a conductive film covering the gate electrode and the first interconnect, and thereafter, patterning the multilayer film of the first insulating film and the conductive film to form a contact hole at a position overlapping the first interconnect, thereby forming a gate insulating film;

a source layer formation step of patterning the conductive film to form a source electrode and a drain electrode overlapping the gate electrode and separated apart from each other, and a second interconnect intersecting the first interconnect at the position of the contact hole;

an interlayer insulating film formation step of successively forming an oxide semiconductor film and a second insulating film covering the source electrode, the drain electrode, and the second interconnect, and thereafter, patterning the second insulating film to form an interlayer insulating film; and

a pixel electrode formation step of reducing the resistance of the oxide semiconductor film exposed through the interlayer insulating film to form a pixel electrode, and causing the first and second interconnects to be conductive.

5. The method of claim 4, wherein

the gate insulating film formation step includes a step of forming a photosensitive resin film on the conductive film and performing a halftone exposure of the photosensitive resin film to form a resist pattern with a recessed portion, and a step of etching the multilayer film of the first insulating film and the conductive film exposed through the resist pattern to form the contact hole, and

in the source layer formation step, a thickness of the resist pattern is reduced to remove a bottom portion of the recessed portion of the resist pattern to expose the conductive film, and the exposed conductive film is patterned by etching.