LOW-POWER SYSTEM CLOCK CALIBRATION BASED ON A HIGH- ACCURACY REFERENCE CLOCK

• US 20120109259A1
• Filed: 10/29/2010
• Published: 05/03/2012
• Est. Priority Date: 10/29/2010
• Status: Active Grant

• Current Assignee: Medtronic Incorporated (Medtronic Plc)
• Original Assignee: Medtronic Incorporated (Medtronic Plc)
• Inventors: Gordon, Charles R., Reinke, James D., Roberts, Jonathan P., Bond, Matthew, Liang, Weizheng
• Granted Patent: US 8,825,170 B2
• Time in Patent Office: Days
• US Class Current: 607/60
• CPC Class Codes: A61N 1/025 Digital circuitry features of electrotherapy devices, e.g. memory, clocks, processors
• CPC Class Codes: A61N 1/372 Arrangements in connection with the implantation of stimulators
• CPC Class Codes: A61N 1/37264 Changing the program; Upgrading firmware
• CPC Class Codes: A61N 1/37276 characterised by means for reducing power consumption during telemetry
• CPC Class Codes: G06F 1/04 Generating or distributing clock signals or signals derived directly therefrom
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators

Abstract

Various techniques are described for periodically performing a calibration routine to calibrate a low-power system clock within an implantable medical device (IMD) based on a high accuracy reference clock also included in the IMD. The system clock is powered continuously, and the reference clock is only powered on during the calibration routine. The techniques include determining a clock error of the system clock based on a difference between frequencies of the system clock and the reference clock over a fixed number of clock cycles, and adjusting a trim value of the system clock to compensate for the clock error. Calibrating the system clock with a delta-sigma loop, for example, reduces the clock error over time. This allows accurate adjustment of the system clock to compensate for errors due to trim resolution, circuit noise and temperature.

Claims

1. An implantable medical device (IMD) comprising:

a processor;

a system clock that comprises a low power oscillator, according to which the processor operates the IMD;

a reference clock that comprises a high accuracy oscillator; and

a clock calibrator that periodically performs a calibration routine to calibrate the system clock based on the reference clock, wherein the system clock is continuously powered and the reference clock is powered during the calibration routine.

2. The IMD of claim 1, wherein the clock calibrator comprises:

a controller that powers on the reference clock at a start of the calibration routine, and disables the reference clock at an end of the calibration routine;

a clock comparator that determines a clock error of the system clock based on a difference between frequencies of the system clock and the reference clock over a fixed number of clock cycles of the system clock; and

a clock adjuster that adjusts a trim value of the system clock to compensate for the clock error.

3. The IMD of claim 2, wherein the clock comparator includes:

a system clock counter that is set equal to the fixed number of clock cycles and decrements by one for each clock cycle of the system clock, wherein the system clock counter stops when equal to zero; and

a reference clock counter that is set equal to the fixed number of clock cycles and decrements by one for each clock cycle of the reference clock, wherein the reference clock counter stops at a reference count value when the system clock counter is equal to zero, wherein the reference count value is indicative of the clock error of the system clock.

4. The IMD of claim 2, wherein the clock calibrator performs the calibration routine with a delta-sigma loop, and wherein the clock adjuster integrates the clock error over time to calculate a cumulative clock error of the system clock, and adjusts the trim value of the system clock based on a magnitude and sign of the cumulative clock error.

5. The IMD of claim 1, further comprising:

a telemetry module; and

a telemetry polling clock, according to which the telemetry module monitors for a telemetry downlink,

wherein the clock calibrator periodically performs the calibration routine to simultaneously calibrate the system clock and the telemetry polling clock based on the reference clock.

6. The IMD of claim 1, further comprising:

a telemetry module; and

a telemetry linking clock, according to which the telemetry module performs a telemetry session once a telemetry downlink is present, and

wherein the clock calibrator continuously performs a calibration routine to calibrate the telemetry linking clock based on the reference clock during the telemetry session, wherein the reference clock is powered continuously during the telemetry session.

7. The IMD of claim 1, wherein the clock calibrator periodically performs the calibration routine according to a calibration period set equal to one of 3.75 minutes, 7 minutes, 15 minutes, 30 minutes and 60 minutes.

8. The IMD of claim 1, wherein the reference clock comprises a crystal oscillator.

9. The IMD of claim 1, wherein the system clock and the reference clock operate at a same clock frequency value.

10. A method comprising:

operating an implantable medical device (IMD) in accordance with a system clock that comprises a low power oscillator clock included in the IMD; and

periodically performing a calibration routine to calibrate the system clock based on the reference clock, wherein the system clock is continuously powered and the reference clock is powered during the calibration routine.

11. The method of claim 10, wherein periodically performing a calibration routine to calibrate the system clock further comprises:

powering on the reference clock at a start of the calibration routine;

determining a clock error of the system clock based on a difference between frequencies of the system clock and the reference clock over a fixed number of clock cycles of the system clock;

adjusting a trim value of the system clock to compensate for the clock error; and

disabling the reference clock at an end of the calibration routine.

12. The method of claim 11, wherein determining a clock error of the system clock further comprises:

setting a system clock counter and a reference clock counter equal to the fixed number of clock cycles;

decrementing the system clock counter by one for each clock cycle of the system clock, wherein the system clock counter stops when equal to zero; and

decrementing the reference clock counter by one for each clock cycle of the reference clock, wherein the reference clock counter stops at a reference count value when the system clock counter is equal to zero, wherein the reference count value is indicative of the clock error of the system clock.

13. The method of claim 11, wherein periodically performing a calibration routine to calibrate the system clock further comprises periodically performing a calibration routine with a delta-sigma loop, the method further comprising:

integrating the clock error over time to calculate a cumulative clock cycle error of the system clock; and

adjusting the trim value of the system clock based on a magnitude and sign of the cumulative clock error.

14. The method of claim 10, further comprising:

monitoring for a telemetry downlink with a telemetry module included in the IMD in accordance with a telemetry polling clock included in the IMD; and

periodically performing the calibration routine to simultaneously calibrate the system clock and the telemetry polling clock based on the reference clock.

15. The method of claim 10, further comprising:

performing a telemetry session with a telemetry module included in the IMD in accordance with a telemetry linking clock included in the IMD once a telemetry downlink is present; and

continuously performing a calibration routine to calibrate the telemetry linking clock based on the reference clock during the telemetry session, wherein the reference clock is powered continuously during the telemetry session.

16. The method of claim 10, wherein periodically performing a calibration routine with a delta-sigma loop to calibrate the system clock comprises periodically performing the calibration routine according to a calibration period set equal to one of 3.75 minutes, 7 minutes, 15 minutes, 30 minutes and 60 minutes.

17. The method of claim 10, wherein the reference clock comprises a crystal oscillator.

18. The method of claim 10, wherein the system clock and the reference clock operate at a same clock frequency value.

19. An implantable medical device (IMD) comprising:

a system clock that comprises a low power oscillator;

a reference clock that comprises a high accuracy oscillator;

means for operating the IMD in accordance with the system clock; and

means for periodically performing a calibration routine to calibrate the system clock based on the reference clock, wherein the system clock is continuously powered and the reference clock is powered during the calibration routine.

20. The IMD of claim 19, further comprising:

means for powering on the reference clock at a start of the calibration routine;

means for determining a clock error of the system clock based on a difference between frequencies of the system clock and the reference clock over a fixed number of clock cycles of the system clock;

means for adjusting a trim value of the system clock to compensate for the clock error; and

means for disabling the reference clock at an end of the calibration routine.

21. The IMD of claim 20, wherein means for determining a clock error of the system clock further comprise:

means for setting a system clock counter and a reference clock counter equal to the fixed number of clock cycles;

means for decrementing the system clock counter by one for each clock cycle of the system clock, wherein the system clock counter stops when equal to zero; and

means for decrementing the reference clock counter by one for each clock cycle of the reference clock, wherein the reference clock counter stops at a reference count value when the system clock counter is equal to zero, wherein the reference count value is indicative of the clock error of the system clock.

22. The IMD of claim 20, wherein means for periodically performing a calibration routine to calibrate the system clock further comprise means for periodically performing a calibration routine with a delta-sigma loop, the IMD further comprising:

means for integrating the clock error over time to calculate a cumulative clock error of the system clock; and

means for adjusting the trim value of the system clock based on a magnitude and sign of the cumulative clock error.

23. The IMD of claim 19, further comprising:

a telemetry polling clock;

means for monitoring for a telemetry downlink in accordance with the telemetry polling clock; and

means for periodically performing the calibration routine to simultaneously calibrate the system clock and the telemetry polling clock based on the reference clock.

24. The IMD of claim 19, further comprising:

a telemetry linking clock;

means for performing a telemetry session in accordance with the telemetry linking clock once a telemetry downlink is present; and

means for continuously performing a calibration routine to calibrate the telemetry linking clock based on the reference clock during the telemetry session, wherein the reference clock is powered continuously during the telemetry session.

25. The IMD of claim 19, wherein means for periodically performing a calibration routine to calibrate the system clock further comprise means for periodically performing the calibration routine according to a calibration period set equal to one of 3.75 minutes, 7 minutes, 15 minutes, 30 minutes and 60 minutes.

26. The IMD of claim 19, wherein the reference clock comprises a crystal oscillator.

27. The IMD of claim 19, wherein the system clock and the reference clock operate at a same clock frequency value.

28. A computer-readable storage medium comprising instructions that, when executed, cause a programmable processor to:

operate an implantable medical device (IMD) in accordance with a system clock that comprises a low power oscillator clock included in the IMD; and

periodically perform a calibration routine to calibrate the system clock based on the reference clock, wherein the system clock is continuously powered and the reference clock is powered during the calibration routine.

29. The computer-readable storage medium of claim 28, further comprising instructions that cause the programmable processor to:

power on the reference clock at a start of the calibration routine;

determine a clock error of the system clock based on a difference between frequencies of the system clock and the reference clock over a fixed number of clock cycles of the system clock;

adjust a trim value of the system clock to compensate for the clock error; and

disable the reference clock at an end of the calibration routine.

30. The computer-readable storage medium of claim 29, wherein instructions that cause the programmable processor to determine a clock error of the system clock further comprise instruction that cause the programmable processor to:

set a system clock counter and a reference clock counter equal to the fixed number of clock cycles;

decrement the system clock counter by one for each clock cycle of the system clock, wherein the system clock counter stops when equal to zero; and

decrement the reference clock counter by one for each clock cycle of the reference clock, wherein the reference clock counter stops at a reference count value when the system clock counter is equal to zero, wherein the reference count value is indicative of the clock error of the system clock.

31. The computer-readable storage medium of claim 29, wherein instructions that cause the programmable processor to periodically perform a calibration routine to calibrate the system clock further comprise instructions that cause the programmable processor to periodically perform a calibration routine with a delta-sigma loop, further comprising instructions that cause the programmable processor to:

integrate the clock error over time to calculate a cumulative clock error of the system clock; and

adjust a trim value of the system clock based on a magnitude and sign of the cumulative clock error.

32. The computer-readable medium of claim 28, further comprising instructions that cause the programmable processor to:

monitor for a telemetry downlink with a telemetry module included in the IMD in accordance with a telemetry polling clock included in the IMD; and

periodically perform the calibration routine to simultaneously calibrate the system clock and the telemetry polling clock based on the reference clock.

33. The computer-readable medium of claim 28, further comprising instructions that cause the programmable processor to:

perform a telemetry session with a telemetry module included in the IMD in accordance with a telemetry linking clock included in the IMD once a telemetry downlink is present; and

continuously perform a calibration routine to calibrate the telemetry linking clock based on the reference clock during the telemetry session, wherein the reference clock is powered continuously during the telemetry session.

34. The computer-readable medium of claim 28, wherein instructions that cause the programmable processor to periodically perform a calibration routine with a delta-sigma loop to calibrate the system clock further comprise instruction that cause the programmable processor to periodically perform the calibration routine according to a calibration period set equal to one of 3.75 minutes, 7 minutes, 15 minutes, 30 minutes and 60 minutes.

35. The computer-readable medium of claim 28, wherein the reference clock comprises a crystal oscillator.

36. The computer-readable medium of claim 28, wherein the system clock and the reference clock operate at a same clock frequency value.